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[PATCH 26/70] target/m68k: Avoid tcg_const_i32 when modified
From: |
Richard Henderson |
Subject: |
[PATCH 26/70] target/m68k: Avoid tcg_const_i32 when modified |
Date: |
Sun, 26 Feb 2023 19:41:49 -1000 |
In several instances, a temp is initialized with a
for use as a constant, and then subsequently used
as an unrelated temp. Split them.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/m68k/translate.c | 29 ++++++++++++++++-------------
1 file changed, 16 insertions(+), 13 deletions(-)
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index 7435e51acc..6f4151232f 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -1635,8 +1635,8 @@ static void bcd_add(TCGv dest, TCGv src)
* = result with some possible exceeding 0x6
*/
- t0 = tcg_const_i32(0x066);
- tcg_gen_add_i32(t0, t0, src);
+ t0 = tcg_temp_new();
+ tcg_gen_addi_i32(t0, src, 0x066);
t1 = tcg_temp_new();
tcg_gen_add_i32(t1, t0, dest);
@@ -1822,7 +1822,8 @@ DISAS_INSN(nbcd)
SRC_EA(env, src, OS_BYTE, 0, &addr);
- dest = tcg_const_i32(0);
+ dest = tcg_temp_new();
+ tcg_gen_movi_i32(dest, 0);
bcd_sub(dest, src);
DEST_EA(env, insn, OS_BYTE, dest, &addr);
@@ -1900,8 +1901,8 @@ DISAS_INSN(bitop_reg)
else
tcg_gen_andi_i32(src2, DREG(insn, 9), 31);
- tmp = tcg_const_i32(1);
- tcg_gen_shl_i32(tmp, tmp, src2);
+ tmp = tcg_temp_new();
+ tcg_gen_shl_i32(tmp, tcg_constant_i32(1), src2);
tcg_gen_and_i32(QREG_CC_Z, src1, tmp);
@@ -3080,7 +3081,7 @@ DISAS_INSN(suba)
static inline void gen_subx(DisasContext *s, TCGv src, TCGv dest, int opsize)
{
- TCGv tmp;
+ TCGv tmp, zero;
gen_flush_flags(s); /* compute old Z */
@@ -3089,14 +3090,15 @@ static inline void gen_subx(DisasContext *s, TCGv src,
TCGv dest, int opsize)
* (X, N) = dest - (src + X);
*/
- tmp = tcg_const_i32(0);
- tcg_gen_add2_i32(QREG_CC_N, QREG_CC_X, src, tmp, QREG_CC_X, tmp);
- tcg_gen_sub2_i32(QREG_CC_N, QREG_CC_X, dest, tmp, QREG_CC_N, QREG_CC_X);
+ zero = tcg_constant_i32(0);
+ tcg_gen_add2_i32(QREG_CC_N, QREG_CC_X, src, zero, QREG_CC_X, zero);
+ tcg_gen_sub2_i32(QREG_CC_N, QREG_CC_X, dest, zero, QREG_CC_N, QREG_CC_X);
gen_ext(QREG_CC_N, QREG_CC_N, opsize, 1);
tcg_gen_andi_i32(QREG_CC_X, QREG_CC_X, 1);
/* Compute signed-overflow for subtract. */
+ tmp = tcg_temp_new();
tcg_gen_xor_i32(QREG_CC_V, QREG_CC_N, dest);
tcg_gen_xor_i32(tmp, dest, src);
tcg_gen_and_i32(QREG_CC_V, QREG_CC_V, tmp);
@@ -3283,7 +3285,7 @@ DISAS_INSN(adda)
static inline void gen_addx(DisasContext *s, TCGv src, TCGv dest, int opsize)
{
- TCGv tmp;
+ TCGv tmp, zero;
gen_flush_flags(s); /* compute old Z */
@@ -3292,13 +3294,14 @@ static inline void gen_addx(DisasContext *s, TCGv src,
TCGv dest, int opsize)
* (X, N) = src + dest + X;
*/
- tmp = tcg_const_i32(0);
- tcg_gen_add2_i32(QREG_CC_N, QREG_CC_X, QREG_CC_X, tmp, dest, tmp);
- tcg_gen_add2_i32(QREG_CC_N, QREG_CC_X, QREG_CC_N, QREG_CC_X, src, tmp);
+ zero = tcg_constant_i32(0);
+ tcg_gen_add2_i32(QREG_CC_N, QREG_CC_X, QREG_CC_X, zero, dest, zero);
+ tcg_gen_add2_i32(QREG_CC_N, QREG_CC_X, QREG_CC_N, QREG_CC_X, src, zero);
gen_ext(QREG_CC_N, QREG_CC_N, opsize, 1);
/* Compute signed-overflow for addition. */
+ tmp = tcg_temp_new();
tcg_gen_xor_i32(QREG_CC_V, QREG_CC_N, src);
tcg_gen_xor_i32(tmp, dest, src);
tcg_gen_andc_i32(QREG_CC_V, QREG_CC_V, tmp);
--
2.34.1
- [PATCH 16/70] target/hexagon/idef-parser: Use gen_tmp for LPCFG, (continued)
- [PATCH 16/70] target/hexagon/idef-parser: Use gen_tmp for LPCFG, Richard Henderson, 2023/02/27
- [PATCH 18/70] target/hexagon/idef-parser: Use gen_tmp for gen_rvalue_pred, Richard Henderson, 2023/02/27
- [PATCH 20/70] target/hppa: Avoid tcg_const_i64 in trans_fid_f, Richard Henderson, 2023/02/27
- [PATCH 21/70] target/hppa: Avoid use of tcg_const_i32 throughout, Richard Henderson, 2023/02/27
- [PATCH 19/70] target/hexagon/idef-parser: Use gen_constant for gen_extend_tcg_width_op, Richard Henderson, 2023/02/27
- [PATCH 22/70] target/i386: Simplify POPF, Richard Henderson, 2023/02/27
- [PATCH 23/70] target/i386: Avoid use of tcg_const_* throughout, Richard Henderson, 2023/02/27
- [PATCH 24/70] target/m68k: Reject immediate as destination in gen_ea_mode, Richard Henderson, 2023/02/27
- [PATCH 25/70] target/m68k: Use tcg_constant_i32 in gen_ea_mode, Richard Henderson, 2023/02/27
- [PATCH 26/70] target/m68k: Avoid tcg_const_i32 when modified,
Richard Henderson <=
- [PATCH 27/70] target/m68k: Avoid tcg_const_i32 in bfop_reg, Richard Henderson, 2023/02/27
- [PATCH 30/70] target/mips: Split out gen_lxl, Richard Henderson, 2023/02/27
- [PATCH 28/70] target/m68k: Avoid tcg_const_* throughout, Richard Henderson, 2023/02/27
- [PATCH 29/70] target/microblaze: Avoid tcg_const_* throughout, Richard Henderson, 2023/02/27
- [PATCH 32/70] target/mips: Avoid tcg_const_tl in gen_r6_ld, Richard Henderson, 2023/02/27
- [PATCH 33/70] target/mips: Avoid tcg_const_* throughout, Richard Henderson, 2023/02/27
- [PATCH 31/70] target/mips: Split out gen_lxr, Richard Henderson, 2023/02/27
- [PATCH 34/70] target/ppc: Split out gen_vx_vmul10, Richard Henderson, 2023/02/27
- [PATCH 35/70] target/ppc: Avoid tcg_const_i64 in do_vector_shift_quad, Richard Henderson, 2023/02/27