[PATCH v2 00/10] target/arm: Implement FEAT_PMUv3p5

[Peter Maydell]

This patchset implements the Armv8.5 feature FEAT_PMUv3p5, which is
a set of minor enhancements to the PMU:
 * EL2 and EL3 can now prohibit the cycle counter from counting
   when in EL2 or when Secure, using new MDCR_EL2.HCCD and
   MDCR_EL3.SCCD bits
 * event counters are now 64 bits, with the overflow detection
   configurably at the 32 bit or 64 bit mark

It also fixes a set of bugs in the existing PMU emulation which I
discovered while trying to test my additions.

This is of course all intended for 7.2.

Changes v1->v2:
 * fixed indent error, comment typo
 * a non-change: opted not to use bitwise |= for bool
 * fixed patch 8 to implement MDCR_EL3.SCCD, not some
   weird mix of MCCD and SCCD
 * update emulation.rst to note feature is implemented

Patch 8 is the only one that needs review.

thanks
-- PMM

Peter Maydell (10):
  target/arm: Don't corrupt high half of PMOVSR when cycle counter
    overflows
  target/arm: Correct value returned by pmu_counter_mask()
  target/arm: Don't mishandle count when enabling or disabling PMU
    counters
  target/arm: Ignore PMCR.D when PMCR.LC is set
  target/arm: Honour MDCR_EL2.HPMD in Secure EL2
  target/arm: Detect overflow when calculating next PMU interrupt
  target/arm: Rename pmu_8_n feature test functions
  target/arm: Implement FEAT_PMUv3p5 cycle counter disable bits
  target/arm: Support 64-bit event counters for FEAT_PMUv3p5
  target/arm: Report FEAT_PMUv3p5 for TCG '-cpu max'

 docs/system/arm/emulation.rst |   1 +
 target/arm/cpu.h              |  37 +++++--
 target/arm/internals.h        |   5 +-
 target/arm/cpu64.c            |   2 +-
 target/arm/cpu_tcg.c          |   2 +-
 target/arm/helper.c           | 198 +++++++++++++++++++++++++++-------
 6 files changed, 192 insertions(+), 53 deletions(-)

-- 
2.25.1