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Re: [PATCH 10/10] target/arm: Report FEAT_PMUv3p5 for TCG '-cpu max'
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From: |
Peter Maydell |
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Subject: |
Re: [PATCH 10/10] target/arm: Report FEAT_PMUv3p5 for TCG '-cpu max' |
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Date: |
Thu, 11 Aug 2022 18:26:06 +0100 |
On Thu, 11 Aug 2022 at 18:16, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> Update the ID registers for TCG's '-cpu max' to report a FEAT_PMUv3p5
> compliant PMU.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Oops, forgot the docs update:
--- a/docs/system/arm/emulation.rst
+++ b/docs/system/arm/emulation.rst
@@ -52,6 +52,7 @@ the following architecture extensions:
- FEAT_PMULL (PMULL, PMULL2 instructions)
- FEAT_PMUv3p1 (PMU Extensions v3.1)
- FEAT_PMUv3p4 (PMU Extensions v3.4)
+- FEAT_PMUv3p5 (PMU Extensions v3.5)
- FEAT_RAS (Reliability, availability, and serviceability)
- FEAT_RASv1p1 (RAS Extension v1.1)
- FEAT_RDM (Advanced SIMD rounding double multiply accumulate instructions)
thanks
-- PMM
- Re: [PATCH 05/10] target/arm: Honour MDCR_EL2.HPMD in Secure EL2, (continued)
- [PATCH 08/10] target/arm: Implement FEAT_PMUv3p5 cycle counter disable bits, Peter Maydell, 2022/08/11
- [PATCH 03/10] target/arm: Don't mishandle count when enabling or disabling PMU counters, Peter Maydell, 2022/08/11
- [PATCH 06/10] target/arm: Detect overflow when calculating next PMU interrupt, Peter Maydell, 2022/08/11
- [PATCH 10/10] target/arm: Report FEAT_PMUv3p5 for TCG '-cpu max', Peter Maydell, 2022/08/11
- Re: [PATCH 10/10] target/arm: Report FEAT_PMUv3p5 for TCG '-cpu max',
Peter Maydell <=
- [PATCH 07/10] target/arm: Rename pmu_8_n feature test functions, Peter Maydell, 2022/08/11
- [PATCH 09/10] target/arm: Support 64-bit event counters for FEAT_PMUv3p5, Peter Maydell, 2022/08/11