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Re: [RFC 0/3] Add Generic SPI GPIO model
From: |
Andrew Jeffery |
Subject: |
Re: [RFC 0/3] Add Generic SPI GPIO model |
Date: |
Mon, 01 Aug 2022 11:49:09 +0930 |
User-agent: |
Cyrus-JMAP/3.7.0-alpha0-758-ge0d20a54e1-fm-20220729.001-ge0d20a54 |
On Sun, 31 Jul 2022, at 06:48, Cédric Le Goater wrote:
> On 7/29/22 19:30, Peter Delevoryas wrote:
>> Certainly we'd like to use IRQ's instead, but she ran into correctness
>> problems. Maybe we can investigate that further and fix it.
Yes, let's not work around problems that we have the ability to fix.
>
> So much is happening in that mode.
Yes, though while there's no-doubt accidental complexity in terms of
its implementation, the underlying hardware is also quite haphazard and
we need an approach that scales to the large number of GPIOs it
provides. So I'd argue there's a bunch of essential complexity involved
as well.
Do we start with a fresh implementation that allows us to get the
expected behaviour and then build that out to replace the current
implementation?
Or, can we add more tests for the existing model to pin down where the
bugs are?
> We need more trace events in the Aspeed
> GPIO model at least an extra in aspeed_gpio_update()
We can always fall back to this but my hope is we can get better test
coverage to iron out the bugs. Maybe that gets us a more refined and
maintainable model implementation along the way.
Cheers,
Andrew
- [RFC 1/3] hw: m25p80: add prereading ability in transfer8, (continued)