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[PATCH 2/7] target/arm: Calculate mask/base_mask in get_level1_table_add
From: |
Peter Maydell |
Subject: |
[PATCH 2/7] target/arm: Calculate mask/base_mask in get_level1_table_address() |
Date: |
Thu, 14 Jul 2022 14:22:58 +0100 |
In get_level1_table_address(), instead of using precalculated values
of mask and base_mask from the TCR struct, calculate them directly
(in the same way we currently do in vmsa_ttbcr_raw_write() to
populate the TCR struct fields).
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/ptw.c | 14 +++++++++-----
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 0d7e8ffa41b..16226d14233 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -315,20 +315,24 @@ static bool get_level1_table_address(CPUARMState *env,
ARMMMUIdx mmu_idx,
uint32_t *table, uint32_t address)
{
/* Note that we can only get here for an AArch32 PL0/PL1 lookup */
- TCR *tcr = regime_tcr(env, mmu_idx);
+ uint64_t tcr = regime_tcr_value(env, mmu_idx);
+ int maskshift = extract32(tcr, 0, 3);
+ uint32_t mask = ~(((uint32_t)0xffffffffu) >> maskshift);
+ uint32_t base_mask;
- if (address & tcr->mask) {
- if (tcr->raw_tcr & TTBCR_PD1) {
+ if (address & mask) {
+ if (tcr & TTBCR_PD1) {
/* Translation table walk disabled for TTBR1 */
return false;
}
*table = regime_ttbr(env, mmu_idx, 1) & 0xffffc000;
} else {
- if (tcr->raw_tcr & TTBCR_PD0) {
+ if (tcr & TTBCR_PD0) {
/* Translation table walk disabled for TTBR0 */
return false;
}
- *table = regime_ttbr(env, mmu_idx, 0) & tcr->base_mask;
+ base_mask = ~((uint32_t)0x3fffu >> maskshift);
+ *table = regime_ttbr(env, mmu_idx, 0) & base_mask;
}
*table |= (address >> 18) & 0x3ffc;
return true;
--
2.25.1
- [PATCH 0/7] target/arm: Handle VTCR_EL2 bits shared between S and NS EL2, Peter Maydell, 2022/07/14
- [PATCH 2/7] target/arm: Calculate mask/base_mask in get_level1_table_address(),
Peter Maydell <=
- [PATCH 1/7] target/arm: Define and use new regime_tcr_value() function, Peter Maydell, 2022/07/14
- [PATCH 3/7] target/arm: Fold regime_tcr() and regime_tcr_value() together, Peter Maydell, 2022/07/14
- [PATCH 4/7] target/arm: Fix big-endian host handling of VTCR, Peter Maydell, 2022/07/14
- [PATCH 5/7] target/arm: Store VTCR_EL2, VSTCR_EL2 registers as uint64_t, Peter Maydell, 2022/07/14
- [PATCH 6/7] target/arm: Store TCR_EL* registers as uint64_t, Peter Maydell, 2022/07/14