[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[RISU PATCH v4 11/29] Always write for --master
From: |
Richard Henderson |
Subject: |
[RISU PATCH v4 11/29] Always write for --master |
Date: |
Fri, 8 Jul 2022 21:16:42 +0530 |
For trace, master of course must write to the file we create.
For sockets, we can report mismatches from either end. At present,
we are reporting mismatches from master. Reverse that so that we
report mismatches from the apprentice, just as we do for trace.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
risu.h | 2 +-
reginfo.c | 38 ++++++++--------------
risu.c | 96 ++++++++++++++++++++++++++-----------------------------
3 files changed, 61 insertions(+), 75 deletions(-)
diff --git a/risu.h b/risu.h
index c83b803..f383b64 100644
--- a/risu.h
+++ b/risu.h
@@ -106,7 +106,7 @@ RisuResult recv_and_compare_register_info(void *uc);
* Should return 0 if it was a good match (ie end of test)
* and 1 for a mismatch.
*/
-int report_match_status(bool trace);
+int report_match_status(void);
/* Interface provided by CPU-specific code: */
diff --git a/reginfo.c b/reginfo.c
index fee025e..c37c5df 100644
--- a/reginfo.c
+++ b/reginfo.c
@@ -14,9 +14,8 @@
#include <stdlib.h>
#include "risu.h"
-struct reginfo master_ri, apprentice_ri;
-
-uint8_t apprentice_memblock[MEMBLOCKLEN];
+static struct reginfo master_ri, apprentice_ri;
+static uint8_t master_memblock[MEMBLOCKLEN];
static int mem_used;
static int packet_mismatch;
@@ -82,8 +81,8 @@ RisuResult recv_and_compare_register_info(void *uc)
trace_header_t header;
RisuOp op;
- reginfo_init(&master_ri, uc);
- op = get_risuop(&master_ri);
+ reginfo_init(&apprentice_ri, uc);
+ op = get_risuop(&apprentice_ri);
res = read_buffer(&header, sizeof(header));
if (res != RES_OK) {
@@ -107,7 +106,7 @@ RisuResult recv_and_compare_register_info(void *uc)
/* Do a simple register compare on (a) explicit request
* (b) end of test (c) a non-risuop UNDEF
*/
- res = read_buffer(&apprentice_ri, reginfo_size());
+ res = read_buffer(&master_ri, reginfo_size());
if (res != RES_OK) {
packet_mismatch = 1;
} else if (!reginfo_is_eq(&master_ri, &apprentice_ri)) {
@@ -119,18 +118,18 @@ RisuResult recv_and_compare_register_info(void *uc)
respond(res);
break;
case OP_SETMEMBLOCK:
- memblock = (void *)(uintptr_t)get_reginfo_paramreg(&master_ri);
+ memblock = (void *)(uintptr_t)get_reginfo_paramreg(&apprentice_ri);
break;
case OP_GETMEMBLOCK:
- set_ucontext_paramreg(uc, get_reginfo_paramreg(&master_ri) +
+ set_ucontext_paramreg(uc, get_reginfo_paramreg(&apprentice_ri) +
(uintptr_t)memblock);
break;
case OP_COMPAREMEM:
mem_used = 1;
- res = read_buffer(apprentice_memblock, MEMBLOCKLEN);
+ res = read_buffer(master_memblock, MEMBLOCKLEN);
if (res != RES_OK) {
packet_mismatch = 1;
- } else if (memcmp(memblock, apprentice_memblock, MEMBLOCKLEN) != 0) {
+ } else if (memcmp(memblock, master_memblock, MEMBLOCKLEN) != 0) {
/* memory mismatch */
res = RES_MISMATCH;
}
@@ -149,18 +148,13 @@ RisuResult recv_and_compare_register_info(void *uc)
* Should return 0 if it was a good match (ie end of test)
* and 1 for a mismatch.
*/
-int report_match_status(bool trace)
+int report_match_status(void)
{
int resp = 0;
fprintf(stderr, "match status...\n");
if (packet_mismatch) {
fprintf(stderr, "packet mismatch (probably disagreement "
"about UNDEF on load/store)\n");
- /* We don't have valid reginfo from the apprentice side
- * so stop now rather than printing anything about it.
- */
- fprintf(stderr, "%s reginfo:\n", trace ? "this" : "master");
- reginfo_dump(&master_ri, stderr);
return 1;
}
if (!reginfo_is_eq(&master_ri, &apprentice_ri)) {
@@ -168,7 +162,7 @@ int report_match_status(bool trace)
resp = 1;
}
if (mem_used
- && memcmp(memblock, &apprentice_memblock, MEMBLOCKLEN) != 0) {
+ && memcmp(memblock, &master_memblock, MEMBLOCKLEN) != 0) {
fprintf(stderr, "mismatch on memory!\n");
resp = 1;
}
@@ -177,15 +171,11 @@ int report_match_status(bool trace)
return 0;
}
- fprintf(stderr, "%s reginfo:\n", trace ? "this" : "master");
+ fprintf(stderr, "master reginfo:\n");
reginfo_dump(&master_ri, stderr);
- fprintf(stderr, "%s reginfo:\n", trace ? "trace" : "apprentice");
+ fprintf(stderr, "apprentice reginfo:\n");
reginfo_dump(&apprentice_ri, stderr);
- if (trace) {
- reginfo_dump_mismatch(&apprentice_ri, &master_ri, stderr);
- } else {
- reginfo_dump_mismatch(&master_ri, &apprentice_ri, stderr);
- }
+ reginfo_dump_mismatch(&master_ri, &apprentice_ri, stderr);
return resp;
}
diff --git a/risu.c b/risu.c
index f238117..199f697 100644
--- a/risu.c
+++ b/risu.c
@@ -102,11 +102,7 @@ static void master_sigill(int sig, siginfo_t *si, void *uc)
RisuResult r;
signal_count++;
- if (trace) {
- r = send_register_info(uc);
- } else {
- r = recv_and_compare_register_info(uc);
- }
+ r = send_register_info(uc);
if (r == RES_OK) {
advance_pc(uc);
} else {
@@ -119,11 +115,7 @@ static void apprentice_sigill(int sig, siginfo_t *si, void
*uc)
RisuResult r;
signal_count++;
- if (trace) {
- r = recv_and_compare_register_info(uc);
- } else {
- r = send_register_info(uc);
- }
+ r = recv_and_compare_register_info(uc);
if (r == RES_OK) {
advance_pc(uc);
} else {
@@ -186,61 +178,65 @@ static int master(void)
{
RisuResult res = sigsetjmp(jmpbuf, 1);
- if (res != RES_OK) {
+ switch (res) {
+ case RES_OK:
+ set_sigill_handler(&master_sigill);
+ fprintf(stderr, "starting master image at 0x%"PRIxPTR"\n",
+ image_start_address);
+ fprintf(stderr, "starting image\n");
+ image_start();
+ fprintf(stderr, "image returned unexpectedly\n");
+ return EXIT_FAILURE;
+
+ case RES_END:
#ifdef HAVE_ZLIB
if (trace && comm_fd != STDOUT_FILENO) {
gzclose(gz_trace_file);
}
#endif
close(comm_fd);
- if (trace) {
- fprintf(stderr, "trace complete after %zd checkpoints\n",
- signal_count);
- return EXIT_SUCCESS;
- } else {
- return report_match_status(false);
- }
+ return EXIT_SUCCESS;
+
+ case RES_BAD_IO:
+ fprintf(stderr, "i/o error after %zd checkpoints\n", signal_count);
+ return EXIT_FAILURE;
+
+ default:
+ fprintf(stderr, "unexpected result %d\n", res);
+ return EXIT_FAILURE;
}
- set_sigill_handler(&master_sigill);
- fprintf(stderr, "starting master image at 0x%"PRIxPTR"\n",
- image_start_address);
- fprintf(stderr, "starting image\n");
- image_start();
- fprintf(stderr, "image returned unexpectedly\n");
- return EXIT_FAILURE;
}
static int apprentice(void)
{
RisuResult res = sigsetjmp(jmpbuf, 1);
- if (res != RES_OK) {
-#ifdef HAVE_ZLIB
- if (trace && comm_fd != STDIN_FILENO) {
- gzclose(gz_trace_file);
- }
-#endif
- close(comm_fd);
+ switch (res) {
+ case RES_OK:
+ set_sigill_handler(&apprentice_sigill);
+ fprintf(stderr, "starting apprentice image at 0x%"PRIxPTR"\n",
+ image_start_address);
+ fprintf(stderr, "starting image\n");
+ image_start();
+ fprintf(stderr, "image returned unexpectedly\n");
+ return EXIT_FAILURE;
- switch (res) {
- case RES_END:
- return EXIT_SUCCESS;
- default:
- if (!trace) {
- return EXIT_FAILURE;
- }
- fprintf(stderr, "finished early after %zd checkpoints\n",
- signal_count);
- return report_match_status(true);
- }
+ case RES_END:
+ return EXIT_SUCCESS;
+
+ case RES_MISMATCH:
+ fprintf(stderr, "mismatch after %zd checkpoints\n", signal_count);
+ report_match_status();
+ return EXIT_FAILURE;
+
+ case RES_BAD_IO:
+ fprintf(stderr, "i/o error after %zd checkpoints\n", signal_count);
+ return EXIT_FAILURE;
+
+ default:
+ fprintf(stderr, "unexpected result %d\n", res);
+ return EXIT_FAILURE;
}
- set_sigill_handler(&apprentice_sigill);
- fprintf(stderr, "starting apprentice image at 0x%"PRIxPTR"\n",
- image_start_address);
- fprintf(stderr, "starting image\n");
- image_start();
- fprintf(stderr, "image returned unexpectedly\n");
- return EXIT_FAILURE;
}
static int ismaster;
--
2.34.1
- [RISU PATCH v4 03/29] Hoist trace file and socket opening, (continued)
- [RISU PATCH v4 03/29] Hoist trace file and socket opening, Richard Henderson, 2022/07/08
- [RISU PATCH v4 04/29] Adjust tracefile open for write, Richard Henderson, 2022/07/08
- [RISU PATCH v4 05/29] Use EXIT_FAILURE, EXIT_SUCCESS, Richard Henderson, 2022/07/08
- [RISU PATCH v4 06/29] Make some risu.c symbols static, Richard Henderson, 2022/07/08
- [RISU PATCH v4 07/29] Add enum RisuOp, Richard Henderson, 2022/07/08
- [RISU PATCH v4 08/29] Add enum RisuResult, Richard Henderson, 2022/07/08
- [RISU PATCH v4 09/29] Unify i/o functions and use RisuResult, Richard Henderson, 2022/07/08
- [RISU PATCH v4 10/29] Pass non-OK result back through siglongjmp, Richard Henderson, 2022/07/08
- [RISU PATCH v4 12/29] Simplify syncing with master, Richard Henderson, 2022/07/08
- [RISU PATCH v4 13/29] Split RES_MISMATCH for registers and memory, Richard Henderson, 2022/07/08
- [RISU PATCH v4 11/29] Always write for --master,
Richard Henderson <=
- [RISU PATCH v4 14/29] Merge reginfo.c into risu.c, Richard Henderson, 2022/07/08
- [RISU PATCH v4 15/29] Rearrange reginfo and memblock buffers, Richard Henderson, 2022/07/08
- [RISU PATCH v4 16/29] Split out recv_register_info, Richard Henderson, 2022/07/08
- [RISU PATCH v4 19/29] aarch64: Assume system support for SVE, Richard Henderson, 2022/07/08
- [RISU PATCH v4 17/29] Add magic and size to the trace header, Richard Henderson, 2022/07/08