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[PATCH v5 11/45] target/arm: Mark gather/scatter load/store as non-strea
From: |
Richard Henderson |
Subject: |
[PATCH v5 11/45] target/arm: Mark gather/scatter load/store as non-streaming |
Date: |
Wed, 6 Jul 2022 13:53:37 +0530 |
Mark these as a non-streaming instructions, which should trap
if full a64 support is not enabled in streaming mode.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/sme-fa64.decode | 9 ---------
target/arm/translate-sve.c | 6 ++++++
2 files changed, 6 insertions(+), 9 deletions(-)
diff --git a/target/arm/sme-fa64.decode b/target/arm/sme-fa64.decode
index fe462d2ccc..1acc3ae080 100644
--- a/target/arm/sme-fa64.decode
+++ b/target/arm/sme-fa64.decode
@@ -59,19 +59,10 @@ FAIL 0001 1110 0111 1110 0000 00-- ---- ---- # FJCVTZS
# --11 1100 --1- ---- ---- ---- ---- --10 # Load/store FP register
(register offset)
# --11 1101 ---- ---- ---- ---- ---- ---- # Load/store FP register
(scaled imm)
-FAIL 1000 010- -00- ---- 10-- ---- ---- ---- # SVE2 32-bit gather NT load
(vector+scalar)
FAIL 1000 010- -00- ---- 111- ---- ---- ---- # SVE 32-bit gather prefetch
(vector+imm)
FAIL 1000 0100 0-1- ---- 0--- ---- ---- ---- # SVE 32-bit gather prefetch
(scalar+vector)
-FAIL 1000 010- -01- ---- 1--- ---- ---- ---- # SVE 32-bit gather load
(vector+imm)
-FAIL 1000 0100 0-0- ---- 0--- ---- ---- ---- # SVE 32-bit gather load
byte (scalar+vector)
-FAIL 1000 0100 1--- ---- 0--- ---- ---- ---- # SVE 32-bit gather load
half (scalar+vector)
-FAIL 1000 0101 0--- ---- 0--- ---- ---- ---- # SVE 32-bit gather load
word (scalar+vector)
FAIL 1010 010- ---- ---- 011- ---- ---- ---- # SVE contiguous FF load
(scalar+scalar)
FAIL 1010 010- ---1 ---- 101- ---- ---- ---- # SVE contiguous NF load
(scalar+imm)
FAIL 1010 010- -01- ---- 000- ---- ---- ---- # SVE load & replicate 32
bytes (scalar+scalar)
FAIL 1010 010- -010 ---- 001- ---- ---- ---- # SVE load & replicate 32
bytes (scalar+imm)
FAIL 1100 010- ---- ---- ---- ---- ---- ---- # SVE 64-bit gather
load/prefetch
-FAIL 1110 010- -00- ---- 001- ---- ---- ---- # SVE2 64-bit scatter NT
store (vector+scalar)
-FAIL 1110 010- -10- ---- 001- ---- ---- ---- # SVE2 32-bit scatter NT
store (vector+scalar)
-FAIL 1110 010- ---- ---- 1-0- ---- ---- ---- # SVE scatter store
(scalar+32-bit vector)
-FAIL 1110 010- ---- ---- 101- ---- ---- ---- # SVE scatter store (misc)
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index f8e0716474..b23c6aa0bf 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -5669,6 +5669,7 @@ static bool trans_LD1_zprz(DisasContext *s, arg_LD1_zprz
*a)
if (!dc_isar_feature(aa64_sve, s)) {
return false;
}
+ s->is_nonstreaming = true;
if (!sve_access_check(s)) {
return true;
}
@@ -5700,6 +5701,7 @@ static bool trans_LD1_zpiz(DisasContext *s, arg_LD1_zpiz
*a)
if (!dc_isar_feature(aa64_sve, s)) {
return false;
}
+ s->is_nonstreaming = true;
if (!sve_access_check(s)) {
return true;
}
@@ -5734,6 +5736,7 @@ static bool trans_LDNT1_zprz(DisasContext *s,
arg_LD1_zprz *a)
if (!dc_isar_feature(aa64_sve2, s)) {
return false;
}
+ s->is_nonstreaming = true;
if (!sve_access_check(s)) {
return true;
}
@@ -5857,6 +5860,7 @@ static bool trans_ST1_zprz(DisasContext *s, arg_ST1_zprz
*a)
if (!dc_isar_feature(aa64_sve, s)) {
return false;
}
+ s->is_nonstreaming = true;
if (!sve_access_check(s)) {
return true;
}
@@ -5887,6 +5891,7 @@ static bool trans_ST1_zpiz(DisasContext *s, arg_ST1_zpiz
*a)
if (!dc_isar_feature(aa64_sve, s)) {
return false;
}
+ s->is_nonstreaming = true;
if (!sve_access_check(s)) {
return true;
}
@@ -5921,6 +5926,7 @@ static bool trans_STNT1_zprz(DisasContext *s,
arg_ST1_zprz *a)
if (!dc_isar_feature(aa64_sve2, s)) {
return false;
}
+ s->is_nonstreaming = true;
if (!sve_access_check(s)) {
return true;
}
--
2.34.1
- [PATCH v5 07/45] target/arm: Mark PMULL, FMMLA as non-streaming, (continued)
- [PATCH v5 07/45] target/arm: Mark PMULL, FMMLA as non-streaming, Richard Henderson, 2022/07/06
- [PATCH v5 09/45] target/arm: Mark SMMLA, UMMLA, USMMLA as non-streaming, Richard Henderson, 2022/07/06
- [PATCH v5 03/45] target/arm: Trap non-streaming usage when Streaming SVE is active, Richard Henderson, 2022/07/06
- [PATCH v5 08/45] target/arm: Mark FTSMUL, FTMAD, FADDA as non-streaming, Richard Henderson, 2022/07/06
- [PATCH v5 12/45] target/arm: Mark gather prefetch as non-streaming, Richard Henderson, 2022/07/06
- [PATCH v5 13/45] target/arm: Mark LDFF1 and LDNF1 as non-streaming, Richard Henderson, 2022/07/06
- [PATCH v5 16/45] target/arm: Handle SME in sve_access_check, Richard Henderson, 2022/07/06
- [PATCH v5 04/45] target/arm: Mark ADR as non-streaming, Richard Henderson, 2022/07/06
- [PATCH v5 11/45] target/arm: Mark gather/scatter load/store as non-streaming,
Richard Henderson <=
- [PATCH v5 15/45] target/arm: Add SME enablement checks, Richard Henderson, 2022/07/06
- [PATCH v5 14/45] target/arm: Mark LD1RO as non-streaming, Richard Henderson, 2022/07/06
- [PATCH v5 10/45] target/arm: Mark string/histo/crypto as non-streaming, Richard Henderson, 2022/07/06
- [PATCH v5 17/45] target/arm: Implement SME RDSVL, ADDSVL, ADDSPL, Richard Henderson, 2022/07/06
- [PATCH v5 20/45] target/arm: Implement SME LD1, ST1, Richard Henderson, 2022/07/06
- [PATCH v5 21/45] target/arm: Export unpredicated ld/st from translate-sve.c, Richard Henderson, 2022/07/06
- [PATCH v5 22/45] target/arm: Implement SME LDR, STR, Richard Henderson, 2022/07/06
- [PATCH v5 23/45] target/arm: Implement SME ADDHA, ADDVA, Richard Henderson, 2022/07/06