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[PULL 23/27] hw/i2c: support multiple masters
From: |
Cédric Le Goater |
Subject: |
[PULL 23/27] hw/i2c: support multiple masters |
Date: |
Thu, 30 Jun 2022 13:24:07 +0200 |
From: Klaus Jensen <k.jensen@samsung.com>
Allow slaves to master the bus by registering a bottom halve. If the bus
is busy, the bottom half is queued up. When a slave has succesfully
mastered the bus, the bottom half is scheduled.
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
[ clg : - fixed typos in commit log ]
Message-Id: <20220601210831.67259-4-its@irrelevant.dk>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220630045133.32251-5-me@pjd.dev>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
include/hw/i2c/i2c.h | 14 ++++++++++++++
hw/i2c/core.c | 34 +++++++++++++++++++++++++++++++++-
2 files changed, 47 insertions(+), 1 deletion(-)
diff --git a/include/hw/i2c/i2c.h b/include/hw/i2c/i2c.h
index 5ca3b708c0be..be8bb8b78a60 100644
--- a/include/hw/i2c/i2c.h
+++ b/include/hw/i2c/i2c.h
@@ -69,13 +69,25 @@ struct I2CNode {
QLIST_ENTRY(I2CNode) next;
};
+typedef struct I2CPendingMaster I2CPendingMaster;
+
+struct I2CPendingMaster {
+ QEMUBH *bh;
+ QSIMPLEQ_ENTRY(I2CPendingMaster) entry;
+};
+
typedef QLIST_HEAD(I2CNodeList, I2CNode) I2CNodeList;
+typedef QSIMPLEQ_HEAD(I2CPendingMasters, I2CPendingMaster) I2CPendingMasters;
struct I2CBus {
BusState qbus;
I2CNodeList current_devs;
+ I2CPendingMasters pending_masters;
uint8_t saved_address;
bool broadcast;
+
+ /* Set from slave currently mastering the bus. */
+ QEMUBH *bh;
};
I2CBus *i2c_init_bus(DeviceState *parent, const char *name);
@@ -117,6 +129,8 @@ int i2c_start_send(I2CBus *bus, uint8_t address);
void i2c_end_transfer(I2CBus *bus);
void i2c_nack(I2CBus *bus);
+void i2c_bus_master(I2CBus *bus, QEMUBH *bh);
+void i2c_bus_release(I2CBus *bus);
int i2c_send(I2CBus *bus, uint8_t data);
uint8_t i2c_recv(I2CBus *bus);
bool i2c_scan_bus(I2CBus *bus, uint8_t address, bool broadcast,
diff --git a/hw/i2c/core.c b/hw/i2c/core.c
index d0cb2d32fa44..145dce60782a 100644
--- a/hw/i2c/core.c
+++ b/hw/i2c/core.c
@@ -13,6 +13,7 @@
#include "migration/vmstate.h"
#include "qapi/error.h"
#include "qemu/module.h"
+#include "qemu/main-loop.h"
#include "trace.h"
#define I2C_BROADCAST 0x00
@@ -62,6 +63,7 @@ I2CBus *i2c_init_bus(DeviceState *parent, const char *name)
bus = I2C_BUS(qbus_new(TYPE_I2C_BUS, parent, name));
QLIST_INIT(&bus->current_devs);
+ QSIMPLEQ_INIT(&bus->pending_masters);
vmstate_register(NULL, VMSTATE_INSTANCE_ID_ANY, &vmstate_i2c_bus, bus);
return bus;
}
@@ -74,7 +76,7 @@ void i2c_slave_set_address(I2CSlave *dev, uint8_t address)
/* Return nonzero if bus is busy. */
int i2c_bus_busy(I2CBus *bus)
{
- return !QLIST_EMPTY(&bus->current_devs);
+ return !QLIST_EMPTY(&bus->current_devs) || bus->bh;
}
bool i2c_scan_bus(I2CBus *bus, uint8_t address, bool broadcast,
@@ -180,6 +182,26 @@ int i2c_start_transfer(I2CBus *bus, uint8_t address, bool
is_recv)
: I2C_START_SEND);
}
+void i2c_bus_master(I2CBus *bus, QEMUBH *bh)
+{
+ if (i2c_bus_busy(bus)) {
+ I2CPendingMaster *node = g_new(struct I2CPendingMaster, 1);
+ node->bh = bh;
+
+ QSIMPLEQ_INSERT_TAIL(&bus->pending_masters, node, entry);
+
+ return;
+ }
+
+ bus->bh = bh;
+ qemu_bh_schedule(bus->bh);
+}
+
+void i2c_bus_release(I2CBus *bus)
+{
+ bus->bh = NULL;
+}
+
int i2c_start_recv(I2CBus *bus, uint8_t address)
{
return i2c_do_start_transfer(bus, address, I2C_START_RECV);
@@ -206,6 +228,16 @@ void i2c_end_transfer(I2CBus *bus)
g_free(node);
}
bus->broadcast = false;
+
+ if (!QSIMPLEQ_EMPTY(&bus->pending_masters)) {
+ I2CPendingMaster *node = QSIMPLEQ_FIRST(&bus->pending_masters);
+ bus->bh = node->bh;
+
+ QSIMPLEQ_REMOVE_HEAD(&bus->pending_masters, entry);
+ g_free(node);
+
+ qemu_bh_schedule(bus->bh);
+ }
}
int i2c_send(I2CBus *bus, uint8_t data)
--
2.35.3
- [PULL 13/27] hw/arm/aspeed: add support for the Qualcomm DC-SCM v1 board, (continued)
- [PULL 13/27] hw/arm/aspeed: add support for the Qualcomm DC-SCM v1 board, Cédric Le Goater, 2022/06/30
- [PULL 14/27] hw/arm/aspeed: add Qualcomm Firework BMC machine, Cédric Le Goater, 2022/06/30
- [PULL 15/27] hw/i2c: pmbus: Page #255 is valid page for read requests., Cédric Le Goater, 2022/06/30
- [PULL 17/27] hw/arm/aspeed: Add MAX31785 Fan controllers, Cédric Le Goater, 2022/06/30
- [PULL 16/27] hw/sensor: add Maxim MAX31785 device, Cédric Le Goater, 2022/06/30
- [PULL 18/27] hw/arm/aspeed: firework: Add Thermal Diodes, Cédric Le Goater, 2022/06/30
- [PULL 19/27] hw/arm/aspeed: firework: add I2C MUXes for VR channels, Cédric Le Goater, 2022/06/30
- [PULL 20/27] hw/i2c/aspeed: Fix R_I2CD_FUN_CTRL reference, Cédric Le Goater, 2022/06/30
- [PULL 21/27] hw/i2c/aspeed: Fix DMA len write-enable bit handling, Cédric Le Goater, 2022/06/30
- [PULL 22/27] hw/i2c/aspeed: Fix MASTER_EN missing error message, Cédric Le Goater, 2022/06/30
- [PULL 23/27] hw/i2c: support multiple masters,
Cédric Le Goater <=
- [PULL 25/27] hw/i2c/aspeed: add slave device in old register mode, Cédric Le Goater, 2022/06/30
- [PULL 27/27] hw/misc/aspeed: Add PECI controller, Cédric Le Goater, 2022/06/30
- [PULL 26/27] hw/i2c/aspeed: Add new-registers DMA slave mode RX support, Cédric Le Goater, 2022/06/30
- [PULL 24/27] hw/i2c: add asynchronous send, Cédric Le Goater, 2022/06/30
- Re: [PULL 00/27] aspeed queue, Richard Henderson, 2022/06/30