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Re: [PATCH 29/71] target/arm: Add the SME ZA storage to CPUARMState
From: |
Peter Maydell |
Subject: |
Re: [PATCH 29/71] target/arm: Add the SME ZA storage to CPUARMState |
Date: |
Mon, 6 Jun 2022 17:13:34 +0100 |
On Thu, 2 Jun 2022 at 23:26, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Place this late in the resettable section of the structure,
> to keep the most common element offsets from being > 64k.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/arm/cpu.h | 8 ++++++++
> target/arm/machine.c | 36 ++++++++++++++++++++++++++++++++++++
> 2 files changed, 44 insertions(+)
> diff --git a/target/arm/machine.c b/target/arm/machine.c
> index 285e387d2c..d9dff6576d 100644
> --- a/target/arm/machine.c
> +++ b/target/arm/machine.c
> @@ -167,6 +167,39 @@ static const VMStateDescription vmstate_sve = {
> VMSTATE_END_OF_LIST()
> }
> };
> +
> +static const VMStateDescription vmstate_za_row = {
> + .name = "cpu/sme/za_row",
This isn't a subsection, so it doesn't need to have the hierarchical
name. What it actually is is just the VMStateDescription for
an ARMVectorReg, right? We could give it a name that facilitates
maybe reusing it later if we have other ARMVectorRegs we want to
migrate. (The SVE ones are an awkward special case because of the
overlap with the FP regs.)
> + .version_id = 1,
> + .minimum_version_id = 1,
> + .fields = (VMStateField[]) {
> + VMSTATE_UINT64_ARRAY(d, ARMVectorReg, ARM_MAX_VQ * 2),
> + VMSTATE_END_OF_LIST()
> + }
> +};
> +
> +static bool za_needed(void *opaque)
> +{
> + ARMCPU *cpu = opaque;
> +
> + /*
> + * When ZA storage is disabled, its contents are discarded.
> + * It will be zeroed when ZA storage is re-enabled.
> + */
> + return FIELD_EX64(cpu->env.svcr, SVCR, ZA);
> +}
> +
> +static const VMStateDescription vmstate_za = {
> + .name = "cpu/sme",
> + .version_id = 1,
> + .minimum_version_id = 1,
> + .needed = za_needed,
> + .fields = (VMStateField[]) {
> + VMSTATE_STRUCT_ARRAY(env.zarray, ARMCPU, ARM_MAX_VQ * 16, 0,
> + vmstate_za_row, ARMVectorReg),
> + VMSTATE_END_OF_LIST()
> + }
> +};
> #endif /* AARCH64 */
>
> static bool serror_needed(void *opaque)
> @@ -887,6 +920,9 @@ const VMStateDescription vmstate_arm_cpu = {
> #endif
> &vmstate_serror,
> &vmstate_irq_line_state,
> +#ifdef TARGET_AARCH64
> + &vmstate_za,
> +#endif
> NULL
I don't think there's any requirement for subsections to
be added only at the end of the list, so we could put this
next to the SVE one to avoid the extra ifdef.
thanks
-- PMM
- [PATCH 23/71] target/arm: Add syn_smetrap, (continued)
- [PATCH 23/71] target/arm: Add syn_smetrap, Richard Henderson, 2022/06/02
- [PATCH 25/71] target/arm: Add SVCR, Richard Henderson, 2022/06/02
- [PATCH 24/71] target/arm: Add ARM_CP_SME, Richard Henderson, 2022/06/02
- [PATCH 27/71] target/arm: Add SMIDR_EL1, SMPRI_EL1, SMPRIMAP_EL2, Richard Henderson, 2022/06/02
- [PATCH 29/71] target/arm: Add the SME ZA storage to CPUARMState, Richard Henderson, 2022/06/02
- Re: [PATCH 29/71] target/arm: Add the SME ZA storage to CPUARMState,
Peter Maydell <=
- [PATCH 30/71] target/arm: Implement SMSTART, SMSTOP, Richard Henderson, 2022/06/02
- [PATCH 33/71] target/arm: Generalize cpu_arm_{get,set}_vq, Richard Henderson, 2022/06/02
- [PATCH 31/71] target/arm: Move error for sve%d property to arm_cpu_sve_finalize, Richard Henderson, 2022/06/02
- [PATCH 32/71] target/arm: Create ARMVQMap, Richard Henderson, 2022/06/02
- [PATCH 35/71] target/arm: Move arm_cpu_*_finalize to internals.h, Richard Henderson, 2022/06/02