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[PATCH 003/114] target/arm: Use TRANS_FEAT for gen_gvec_ool_zz
From: |
Richard Henderson |
Subject: |
[PATCH 003/114] target/arm: Use TRANS_FEAT for gen_gvec_ool_zz |
Date: |
Fri, 27 May 2022 11:17:16 -0700 |
Convert SVE translation functions using gen_gvec_ool_zz to TRANS_FEAT.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate-sve.c | 39 +++++++++++++-------------------------
1 file changed, 13 insertions(+), 26 deletions(-)
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 903514cb6a..f7e7a569b7 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -1375,16 +1375,12 @@ static bool trans_ADR_u32(DisasContext *s, arg_rrri *a)
*** SVE Integer Misc - Unpredicated Group
*/
-static bool trans_FEXPA(DisasContext *s, arg_rr_esz *a)
-{
- static gen_helper_gvec_2 * const fns[4] = {
- NULL,
- gen_helper_sve_fexpa_h,
- gen_helper_sve_fexpa_s,
- gen_helper_sve_fexpa_d,
- };
- return gen_gvec_ool_zz(s, fns[a->esz], a->rd, a->rn, 0);
-}
+static gen_helper_gvec_2 * const fexpa_fns[4] = {
+ NULL, gen_helper_sve_fexpa_h,
+ gen_helper_sve_fexpa_s, gen_helper_sve_fexpa_d,
+};
+TRANS_FEAT(FEXPA, aa64_sve, gen_gvec_ool_zz,
+ fexpa_fns[a->esz], a->rd, a->rn, 0)
static bool trans_FTSSEL(DisasContext *s, arg_rrr_esz *a)
{
@@ -2418,14 +2414,11 @@ static bool trans_INSR_r(DisasContext *s, arg_rrr_esz
*a)
return true;
}
-static bool trans_REV_v(DisasContext *s, arg_rr_esz *a)
-{
- static gen_helper_gvec_2 * const fns[4] = {
- gen_helper_sve_rev_b, gen_helper_sve_rev_h,
- gen_helper_sve_rev_s, gen_helper_sve_rev_d
- };
- return gen_gvec_ool_zz(s, fns[a->esz], a->rd, a->rn, 0);
-}
+static gen_helper_gvec_2 * const rev_fns[4] = {
+ gen_helper_sve_rev_b, gen_helper_sve_rev_h,
+ gen_helper_sve_rev_s, gen_helper_sve_rev_d
+};
+TRANS_FEAT(REV_v, aa64_sve, gen_gvec_ool_zz, rev_fns[a->esz], a->rd, a->rn, 0)
static bool trans_TBL(DisasContext *s, arg_rrr_esz *a)
{
@@ -8376,14 +8369,8 @@ static bool trans_USDOT_zzzz(DisasContext *s,
arg_USDOT_zzzz *a)
return true;
}
-static bool trans_AESMC(DisasContext *s, arg_AESMC *a)
-{
- if (!dc_isar_feature(aa64_sve2_aes, s)) {
- return false;
- }
- return gen_gvec_ool_zz(s, gen_helper_crypto_aesmc,
- a->rd, a->rd, a->decrypt);
-}
+TRANS_FEAT(AESMC, aa64_sve2_aes, gen_gvec_ool_zz,
+ gen_helper_crypto_aesmc, a->rd, a->rd, a->decrypt)
static bool do_aese(DisasContext *s, arg_rrr_esz *a, bool decrypt)
{
--
2.34.1
- [PATCH 000/114] target/arm: Rewrite sve feature tests, Richard Henderson, 2022/05/27
- [PATCH 001/114] target/arm: Introduce TRANS, TRANS_FEAT, Richard Henderson, 2022/05/27
- [PATCH 002/114] target/arm: Move null function and sve check into gen_gvec_ool_zz, Richard Henderson, 2022/05/27
- [PATCH 003/114] target/arm: Use TRANS_FEAT for gen_gvec_ool_zz,
Richard Henderson <=
- [PATCH 004/114] target/arm: Move null function and sve check into gen_gvec_ool_zzz, Richard Henderson, 2022/05/27
- [PATCH 005/114] target/arm: Introduce gen_gvec_ool_arg_zzz, Richard Henderson, 2022/05/27
- [PATCH 008/114] target/arm: Move null function and sve check into gen_gvec_ool_zzzz, Richard Henderson, 2022/05/27
- [PATCH 007/114] target/arm: Use TRANS_FEAT for do_sve2_zzz_ool, Richard Henderson, 2022/05/27
- [PATCH 009/114] target/arm: Use TRANS_FEAT for gen_gvec_ool_zzzz, Richard Henderson, 2022/05/27
- [PATCH 012/114] target/arm: Use TRANS_FEAT for gen_gvec_ool_arg_zzzz, Richard Henderson, 2022/05/27
- [PATCH 010/114] target/arm: Introduce gen_gvec_ool_arg_zzzz, Richard Henderson, 2022/05/27
- [PATCH 011/114] target/arm: Use TRANS_FEAT for do_sve2_zzzz_ool, Richard Henderson, 2022/05/27
- [PATCH 013/114] target/arm: Rename do_zzxz_ool to gen_gvec_ool_arg_zzxz, Richard Henderson, 2022/05/27
- [PATCH 006/114] target/arm: Use TRANS_FEAT for gen_gvec_ool_arg_zzz, Richard Henderson, 2022/05/27