Re: [PATCH 2/2] target/arm: Use FIELD definitions for CPACR, CPTR_ELx

[Peter Maydell]

On Tue, 10 May 2022 at 01:06, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> We had a few CPTR_* bits defined, but missed quite a few.
> Complete all of the fields up to ARMv9.2.
> Use FIELD_EX64 instead of manual extract32.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  target/arm/cpu.h    | 44 +++++++++++++++++++++++++++++++-----
>  hw/arm/boot.c       |  2 +-
>  target/arm/cpu.c    | 11 ++++++---
>  target/arm/helper.c | 54 ++++++++++++++++++++++-----------------------
>  4 files changed, 75 insertions(+), 36 deletions(-)
>
> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> index b35b117fe7..c44acd8b84 100644
> --- a/target/arm/cpu.h
> +++ b/target/arm/cpu.h
> @@ -1259,11 +1259,45 @@ void pmu_init(ARMCPU *cpu);
>  #define SCTLR_SPINTMASK (1ULL << 62) /* FEAT_NMI */
>  #define SCTLR_TIDCP   (1ULL << 63) /* FEAT_TIDCP1 */
>
> -#define CPTR_TCPAC    (1U << 31)
> -#define CPTR_TTA      (1U << 20)
> -#define CPTR_TFP      (1U << 10)
> -#define CPTR_TZ       (1U << 8)   /* CPTR_EL2 */
> -#define CPTR_EZ       (1U << 8)   /* CPTR_EL3 */
> +/* Bit definitions for CPACR (AArch32 only) */
> +FIELD(CPACR, CP10, 20, 2)
> +FIELD(CPACR, CP11, 22, 2)
> +FIELD(CPACR, TRCDIS, 28, 1)    /* matches CPACR_EL1.TTA */
> +FIELD(CPACR, D32DIS, 31, 1)    /* up to v7; RAZ in v8 */
> +FIELD(CPACR, ASEDIS, 31, 1)

D32DIS is bit 30, not 31.

> +
> +/* Bit definitions for CPACR_EL1 (AArch64 only) */
> +FIELD(CPACR_EL1, ZEN, 16, 2)
> +FIELD(CPACR_EL1, FPEN, 20, 2)
> +FIELD(CPACR_EL1, SMEN, 24, 2)
> +FIELD(CPACR_EL1, TTA, 28, 1)   /* matches CPACR.TRCDIS */
> +
> +/* Bit definitions for HCPTR (AArch32 only) */
> +FIELD(HCPTR, TCP10, 10, 1)
> +FIELD(HCPTR, TCP11, 11, 1)
> +FIELD(HCPTR, TSAE, 15, 1)

This is TASE, not TSAE.

Otherwise
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

thanks
-- PMM