Re: [PATCH v4 41/45] target/arm: Enable FEAT_CSV2_2 for -cpu max

[Richard Henderson]

On 5/3/22 10:10, Peter Maydell wrote:
> On Sun, 1 May 2022 at 08:16, Richard Henderson
> <richard.henderson@linaro.org> wrote:
> > There is no branch prediction in TCG, therefore there is no
> > need to actually include the context number into the predictor.
> > Therefore all we need to do is add the state for SCXTNUM_ELx.
> >
> > Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> > ---
> > v2: Update emulation.rst; clear CSV2_FRAC; use decimal; tidy access_scxtnum.
> > v3: Rely on EL3-no-EL2 squashing during registration.
> > ---
> >   docs/system/arm/emulation.rst |  3 ++
> >   target/arm/cpu.h              | 16 +++++++++
> >   target/arm/cpu64.c            |  3 +-
> >   target/arm/helper.c           | 61 ++++++++++++++++++++++++++++++++++-
> >   4 files changed, 81 insertions(+), 2 deletions(-)
>
> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
>
> (The handling of SCXTNUM_EL0 should Just Work for user-mode-only,
> right?)

Hmm, interesting.

The linux master does not support CSV2_1.2+.  This bit is supposed to be RES1 when the 
feature is not enabled, so when booted with TCG at EL1 access *should* be trapped, when 
the guest kernel is not buggy.  This falls into the

    /* ??? Lots of these bits are not implemented.  */


fixme in sctlr_write.  If the guest kernel is buggy... ya gets what ya gets.

We are particularly sloppy with SCTLR_EL1 with user-only; the res1 bits are not 
set,
which means that we'll expose the register at user-only.

Although context swapping is not an issue for user-only, I think we should not expose the 
value at this time.  It's plausible that the register will *never* be exposed to EL0.  We 
might get, for instance, a prctl to set a new thread/process-level random value instead.

Will provide a minimal user-only fix for v5, and work on sctlr_write another 
day.


r~