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[PATCH v3 57/60] target/arm: Enable FEAT_CSV3 for -cpu max
From: |
Richard Henderson |
Subject: |
[PATCH v3 57/60] target/arm: Enable FEAT_CSV3 for -cpu max |
Date: |
Sun, 17 Apr 2022 10:44:23 -0700 |
This extension concerns cache speculation, which TCG does
not implement. Thus we can trivially enable this feature.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
v2: Update emulation.rst
---
docs/system/arm/emulation.rst | 1 +
target/arm/cpu64.c | 1 +
target/arm/cpu_tcg.c | 1 +
3 files changed, 3 insertions(+)
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
index aebe3be1ba..f75f0fc110 100644
--- a/docs/system/arm/emulation.rst
+++ b/docs/system/arm/emulation.rst
@@ -15,6 +15,7 @@ the following architecture extensions:
- FEAT_CSV2_1p1 (Cache speculation variant 2, version 1.1)
- FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2)
- FEAT_CSV2_2 (Cache speculation variant 2, version 2)
+- FEAT_CSV3 (Cache speculation variant 3)
- FEAT_DIT (Data Independent Timing instructions)
- FEAT_DPB (DC CVAP instruction)
- FEAT_Debugv8p2 (Debug changes for v8.2)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 6ccbcb857d..6139f51267 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -749,6 +749,7 @@ static void aarch64_max_initfn(Object *obj)
t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */
t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */
t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 2); /* FEAT_CSV2_2 */
+ t = FIELD_DP64(t, ID_AA64PFR0, CSV3, 1); /* FEAT_CSV3 */
cpu->isar.id_aa64pfr0 = t;
t = cpu->isar.id_aa64pfr1;
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
index 762b961707..ea4eccddc3 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/cpu_tcg.c
@@ -74,6 +74,7 @@ void aa32_max_features(ARMCPU *cpu)
cpu->isar.id_pfr0 = t;
t = cpu->isar.id_pfr2;
+ t = FIELD_DP32(t, ID_PFR2, CSV3, 1); /* FEAT_CSV3 */
t = FIELD_DP32(t, ID_PFR2, SSBS, 1); /* FEAT_SSBS */
cpu->isar.id_pfr2 = t;
--
2.25.1
- [PATCH v3 50/60] target/arm: Enable SCR and HCR bits for RAS, (continued)
- [PATCH v3 50/60] target/arm: Enable SCR and HCR bits for RAS, Richard Henderson, 2022/04/17
- [PATCH v3 52/60] target/arm: Implement ESB instruction, Richard Henderson, 2022/04/17
- [PATCH v3 53/60] target/arm: Enable FEAT_RAS for -cpu max, Richard Henderson, 2022/04/17
- [PATCH v3 51/60] target/arm: Implement virtual SError exceptions, Richard Henderson, 2022/04/17
- [PATCH v3 54/60] target/arm: Enable FEAT_IESB for -cpu max, Richard Henderson, 2022/04/17
- [PATCH v3 55/60] target/arm: Enable FEAT_CSV2 for -cpu max, Richard Henderson, 2022/04/17
- [PATCH v3 56/60] target/arm: Enable FEAT_CSV2_2 for -cpu max, Richard Henderson, 2022/04/17
- [PATCH v3 57/60] target/arm: Enable FEAT_CSV3 for -cpu max,
Richard Henderson <=
- [PATCH v3 59/60] target/arm: Define cortex-a76, Richard Henderson, 2022/04/17
- [PATCH v3 58/60] target/arm: Enable FEAT_DGH for -cpu max, Richard Henderson, 2022/04/17
- [PATCH v3 60/60] target/arm: Define neoverse-n1, Richard Henderson, 2022/04/17
- Re: [PATCH v3 00/60] target/arm: Cleanups, new features, new cpus, Peter Maydell, 2022/04/22