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[PATCH v3 31/60] target/arm: Name CPSecureState type
From: |
Richard Henderson |
Subject: |
[PATCH v3 31/60] target/arm: Name CPSecureState type |
Date: |
Sun, 17 Apr 2022 10:43:57 -0700 |
Give this enum a name and use in ARMCPRegInfo and add_cpreg_to_hashtable.
Add the enumerator ARM_CP_SECSTATE_BOTH to clarify how 0
is handled in define_one_arm_cp_reg_with_opaque.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/cpregs.h | 7 ++++---
target/arm/helper.c | 3 ++-
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index fe338730ab..3528c0ebb1 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -133,10 +133,11 @@ typedef enum {
* registered entry will only have one to identify whether the entry is secure
* or non-secure.
*/
-enum {
+typedef enum {
+ ARM_CP_SECSTATE_BOTH = 0, /* define one cpreg for each secstate */
ARM_CP_SECSTATE_S = (1 << 0), /* bit[0]: Secure state register */
ARM_CP_SECSTATE_NS = (1 << 1), /* bit[1]: Non-secure state register */
-};
+} CPSecureState;
/*
* Access rights:
@@ -268,7 +269,7 @@ struct ARMCPRegInfo {
/* Access rights: PL*_[RW] */
CPAccessRights access;
/* Security state: ARM_CP_SECSTATE_* bits/values */
- int secure;
+ CPSecureState secure;
/*
* The opaque pointer passed to define_arm_cp_regs_with_opaque() when
* this register was defined: can be used to hand data through to the
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 8b89039667..7c569a569a 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -8503,7 +8503,8 @@ CpuDefinitionInfoList *qmp_query_cpu_definitions(Error
**errp)
}
static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
- void *opaque, CPState state, int secstate,
+ void *opaque, CPState state,
+ CPSecureState secstate,
int crm, int opc1, int opc2,
const char *name)
{
--
2.25.1
- Re: [PATCH v3 30/60] target/arm: Name CPState type, (continued)
- [PATCH v3 36/60] target/arm: Drop EL3 no EL2 fallbacks, Richard Henderson, 2022/04/17
- [PATCH v3 33/60] target/arm: Store cpregs key in the hash table directly, Richard Henderson, 2022/04/17
- [PATCH v3 34/60] target/arm: Cleanup add_cpreg_to_hashtable, Richard Henderson, 2022/04/17
- [PATCH v3 37/60] target/arm: Merge zcr reginfo, Richard Henderson, 2022/04/17
- [PATCH v3 38/60] target/arm: Add isar predicates for FEAT_Debugv8p2, Richard Henderson, 2022/04/17
- [PATCH v3 39/60] target/arm: Adjust definition of CONTEXTIDR_EL2, Richard Henderson, 2022/04/17
- [PATCH v3 31/60] target/arm: Name CPSecureState type,
Richard Henderson <=
- [PATCH v3 32/60] target/arm: Update sysreg fields when redirecting for E2H, Richard Henderson, 2022/04/17
- [PATCH v3 42/60] target/arm: Set ID_DFR0.PerfMon for qemu-system-arm -cpu max, Richard Henderson, 2022/04/17
- [PATCH v3 40/60] target/arm: Move cortex impdef sysregs to cpu_tcg.c, Richard Henderson, 2022/04/17
- [PATCH v3 41/60] target/arm: Update qemu-system-arm -cpu max to cortex-a57, Richard Henderson, 2022/04/17
- [PATCH v3 43/60] target/arm: Split out aa32_max_features, Richard Henderson, 2022/04/17