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[PATCH 23/41] hw/intc/arm_gicv3: Implement new GICv4 redistributor regis
From: |
Peter Maydell |
Subject: |
[PATCH 23/41] hw/intc/arm_gicv3: Implement new GICv4 redistributor registers |
Date: |
Fri, 8 Apr 2022 15:15:32 +0100 |
Implement the new GICv4 redistributor registers: GICR_VPROPBASER
and GICR_VPENDBASER; for the moment we implement these as simple
reads-as-written stubs, together with the necessary migration
and reset handling.
We don't put ID-register checks on the handling of these registers,
because they are all in the only-in-v4 extra register frames, so
they're not accessible in a GICv3.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
GICv4.1 adds two further registers in the new VLPI frame,
as well as changing the layout of VPROPBASER and VPENDBASER,
but we aren't implementing v4.1 yet, just v4.
---
hw/intc/gicv3_internal.h | 21 +++++++++++
include/hw/intc/arm_gicv3_common.h | 3 ++
hw/intc/arm_gicv3_common.c | 22 ++++++++++++
hw/intc/arm_gicv3_redist.c | 56 ++++++++++++++++++++++++++++++
4 files changed, 102 insertions(+)
diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h
index 9720ccf7507..795bf57d2b3 100644
--- a/hw/intc/gicv3_internal.h
+++ b/hw/intc/gicv3_internal.h
@@ -77,6 +77,7 @@
* Redistributor frame offsets from RD_base
*/
#define GICR_SGI_OFFSET 0x10000
+#define GICR_VLPI_OFFSET 0x20000
/*
* Redistributor registers, offsets from RD_base
@@ -109,6 +110,10 @@
#define GICR_IGRPMODR0 (GICR_SGI_OFFSET + 0x0D00)
#define GICR_NSACR (GICR_SGI_OFFSET + 0x0E00)
+/* VLPI redistributor registers, offsets from VLPI_base */
+#define GICR_VPROPBASER (GICR_VLPI_OFFSET + 0x70)
+#define GICR_VPENDBASER (GICR_VLPI_OFFSET + 0x78)
+
#define GICR_CTLR_ENABLE_LPIS (1U << 0)
#define GICR_CTLR_CES (1U << 1)
#define GICR_CTLR_RWP (1U << 3)
@@ -143,6 +148,22 @@ FIELD(GICR_PENDBASER, PTZ, 62, 1)
#define GICR_PROPBASER_IDBITS_THRESHOLD 0xd
+/* These are the GICv4 VPROPBASER and VPENDBASER layouts; v4.1 is different */
+FIELD(GICR_VPROPBASER, IDBITS, 0, 5)
+FIELD(GICR_VPROPBASER, INNERCACHE, 7, 3)
+FIELD(GICR_VPROPBASER, SHAREABILITY, 10, 2)
+FIELD(GICR_VPROPBASER, PHYADDR, 12, 40)
+FIELD(GICR_VPROPBASER, OUTERCACHE, 56, 3)
+
+FIELD(GICR_VPENDBASER, INNERCACHE, 7, 3)
+FIELD(GICR_VPENDBASER, SHAREABILITY, 10, 2)
+FIELD(GICR_VPENDBASER, PHYADDR, 16, 36)
+FIELD(GICR_VPENDBASER, OUTERCACHE, 56, 3)
+FIELD(GICR_VPENDBASER, DIRTY, 60, 1)
+FIELD(GICR_VPENDBASER, PENDINGLAST, 61, 1)
+FIELD(GICR_VPENDBASER, IDAI, 62, 1)
+FIELD(GICR_VPENDBASER, VALID, 63, 1)
+
#define ICC_CTLR_EL1_CBPR (1U << 0)
#define ICC_CTLR_EL1_EOIMODE (1U << 1)
#define ICC_CTLR_EL1_PMHE (1U << 6)
diff --git a/include/hw/intc/arm_gicv3_common.h
b/include/hw/intc/arm_gicv3_common.h
index 40bc404a652..7ff5a1aa5fc 100644
--- a/include/hw/intc/arm_gicv3_common.h
+++ b/include/hw/intc/arm_gicv3_common.h
@@ -179,6 +179,9 @@ struct GICv3CPUState {
uint32_t gicr_igrpmodr0;
uint32_t gicr_nsacr;
uint8_t gicr_ipriorityr[GIC_INTERNAL];
+ /* VLPI_base page registers */
+ uint64_t gicr_vpropbaser;
+ uint64_t gicr_vpendbaser;
/* CPU interface */
uint64_t icc_sre_el1;
diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c
index 18999e3c8bb..14d76d74840 100644
--- a/hw/intc/arm_gicv3_common.c
+++ b/hw/intc/arm_gicv3_common.c
@@ -144,6 +144,25 @@ const VMStateDescription vmstate_gicv3_cpu_sre_el1 = {
}
};
+static bool gicv4_needed(void *opaque)
+{
+ GICv3CPUState *cs = opaque;
+
+ return cs->gic->revision > 3;
+}
+
+const VMStateDescription vmstate_gicv3_gicv4 = {
+ .name = "arm_gicv3_cpu/gicv4",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .needed = gicv4_needed,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT64(gicr_vpropbaser, GICv3CPUState),
+ VMSTATE_UINT64(gicr_vpendbaser, GICv3CPUState),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
static const VMStateDescription vmstate_gicv3_cpu = {
.name = "arm_gicv3_cpu",
.version_id = 1,
@@ -175,6 +194,7 @@ static const VMStateDescription vmstate_gicv3_cpu = {
.subsections = (const VMStateDescription * []) {
&vmstate_gicv3_cpu_virt,
&vmstate_gicv3_cpu_sre_el1,
+ &vmstate_gicv3_gicv4,
NULL
}
};
@@ -444,6 +464,8 @@ static void arm_gicv3_common_reset(DeviceState *dev)
cs->gicr_waker = GICR_WAKER_ProcessorSleep | GICR_WAKER_ChildrenAsleep;
cs->gicr_propbaser = 0;
cs->gicr_pendbaser = 0;
+ cs->gicr_vpropbaser = 0;
+ cs->gicr_vpendbaser = 0;
/* If we're resetting a TZ-aware GIC as if secure firmware
* had set it up ready to start a kernel in non-secure, we
* need to set interrupts to group 1 so the kernel can use them.
diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c
index 9f1fe09a78e..c310d7f8ff2 100644
--- a/hw/intc/arm_gicv3_redist.c
+++ b/hw/intc/arm_gicv3_redist.c
@@ -236,6 +236,23 @@ static MemTxResult gicr_readl(GICv3CPUState *cs, hwaddr
offset,
case GICR_IDREGS ... GICR_IDREGS + 0x2f:
*data = gicv3_idreg(offset - GICR_IDREGS, GICV3_PIDR0_REDIST);
return MEMTX_OK;
+ /*
+ * VLPI frame registers. We don't need a version check for
+ * VPROPBASER and VPENDBASER because gicv3_redist_size() will
+ * prevent pre-v4 GIC from passing us offsets this high.
+ */
+ case GICR_VPROPBASER:
+ *data = extract64(cs->gicr_vpropbaser, 0, 32);
+ return MEMTX_OK;
+ case GICR_VPROPBASER + 4:
+ *data = extract64(cs->gicr_vpropbaser, 32, 32);
+ return MEMTX_OK;
+ case GICR_VPENDBASER:
+ *data = extract64(cs->gicr_vpendbaser, 0, 32);
+ return MEMTX_OK;
+ case GICR_VPENDBASER + 4:
+ *data = extract64(cs->gicr_vpendbaser, 32, 32);
+ return MEMTX_OK;
default:
return MEMTX_ERROR;
}
@@ -379,6 +396,23 @@ static MemTxResult gicr_writel(GICv3CPUState *cs, hwaddr
offset,
"%s: invalid guest write to RO register at offset "
TARGET_FMT_plx "\n", __func__, offset);
return MEMTX_OK;
+ /*
+ * VLPI frame registers. We don't need a version check for
+ * VPROPBASER and VPENDBASER because gicv3_redist_size() will
+ * prevent pre-v4 GIC from passing us offsets this high.
+ */
+ case GICR_VPROPBASER:
+ cs->gicr_vpropbaser = deposit64(cs->gicr_vpropbaser, 0, 32, value);
+ return MEMTX_OK;
+ case GICR_VPROPBASER + 4:
+ cs->gicr_vpropbaser = deposit64(cs->gicr_vpropbaser, 32, 32, value);
+ return MEMTX_OK;
+ case GICR_VPENDBASER:
+ cs->gicr_vpendbaser = deposit64(cs->gicr_vpendbaser, 0, 32, value);
+ return MEMTX_OK;
+ case GICR_VPENDBASER + 4:
+ cs->gicr_vpendbaser = deposit64(cs->gicr_vpendbaser, 32, 32, value);
+ return MEMTX_OK;
default:
return MEMTX_ERROR;
}
@@ -397,6 +431,17 @@ static MemTxResult gicr_readll(GICv3CPUState *cs, hwaddr
offset,
case GICR_PENDBASER:
*data = cs->gicr_pendbaser;
return MEMTX_OK;
+ /*
+ * VLPI frame registers. We don't need a version check for
+ * VPROPBASER and VPENDBASER because gicv3_redist_size() will
+ * prevent pre-v4 GIC from passing us offsets this high.
+ */
+ case GICR_VPROPBASER:
+ *data = cs->gicr_vpropbaser;
+ return MEMTX_OK;
+ case GICR_VPENDBASER:
+ *data = cs->gicr_vpendbaser;
+ return MEMTX_OK;
default:
return MEMTX_ERROR;
}
@@ -418,6 +463,17 @@ static MemTxResult gicr_writell(GICv3CPUState *cs, hwaddr
offset,
"%s: invalid guest write to RO register at offset "
TARGET_FMT_plx "\n", __func__, offset);
return MEMTX_OK;
+ /*
+ * VLPI frame registers. We don't need a version check for
+ * VPROPBASER and VPENDBASER because gicv3_redist_size() will
+ * prevent pre-v4 GIC from passing us offsets this high.
+ */
+ case GICR_VPROPBASER:
+ cs->gicr_vpropbaser = value;
+ return MEMTX_OK;
+ case GICR_VPENDBASER:
+ cs->gicr_vpendbaser = value;
+ return MEMTX_OK;
default:
return MEMTX_ERROR;
}
--
2.25.1
- Re: [PATCH 13/41] hw/intc/arm_gicv3_its: Split out process_its_cmd() physical interrupt code, (continued)
- [PATCH 17/41] hw/intc/arm_gicv3_its: Implement VSYNC, Peter Maydell, 2022/04/08
- [PATCH 11/41] hw/intc/arm_gicv3_its: Factor out "find ITE given devid, eventid", Peter Maydell, 2022/04/08
- [PATCH 15/41] hw/intc/arm_gicv3: Keep pointers to every connected ITS, Peter Maydell, 2022/04/08
- [PATCH 18/41] hw/intc/arm_gicv3_its: Implement INV command properly, Peter Maydell, 2022/04/08
- [PATCH 23/41] hw/intc/arm_gicv3: Implement new GICv4 redistributor registers,
Peter Maydell <=
- [PATCH 28/41] hw/intc/arm_gicv3_redist: Factor out "update hpplpi for all LPIs" logic, Peter Maydell, 2022/04/08
- [PATCH 21/41] hw/intc/arm_gicv3_its: Implement VINVALL, Peter Maydell, 2022/04/08
- [PATCH 19/41] hw/intc/arm_gicv3_its: Implement INV for virtual interrupts, Peter Maydell, 2022/04/08
- [PATCH 20/41] hw/intc/arm_gicv3_its: Implement VMOVI, Peter Maydell, 2022/04/08
- [PATCH 22/41] hw/intc/arm_gicv3: Implement GICv4's new redistributor frame, Peter Maydell, 2022/04/08