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Re: [PATCH 1/3] target/arm: Check VSTCR.SW when assigning the stage 2 ou
From: |
Idan Horowitz |
Subject: |
Re: [PATCH 1/3] target/arm: Check VSTCR.SW when assigning the stage 2 output PA space |
Date: |
Mon, 28 Mar 2022 00:45:51 +0300 |
Rémi Denis-Courmont <remi@remlab.net> wrote:
> The VTCR_EL2 specification says that the NSA bit "behaves as 1 for all
> purposes
> other than reading back the value of the bit when one of the following is
> true
> (...)
> * The value of VTCR_EL2.NSW is 1.
> * The value of VSTCR_EL2.SA is 1."
>
> Sorry but I don't see any reason to check the SW bit here.
That still does not cover the case of NSA=0, NSW=0, SA=0, SW=1.
> --
> Реми Дёни-Курмон
> http://www.remlab.net/
Idan Horowitz
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