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[PATCH v3 12/17] target/arm: Introduce tlbi_aa64_get_range
From: |
Richard Henderson |
Subject: |
[PATCH v3 12/17] target/arm: Introduce tlbi_aa64_get_range |
Date: |
Wed, 23 Feb 2022 12:31:32 -1000 |
Merge tlbi_aa64_range_get_length and tlbi_aa64_range_get_base,
returning a structure containing both results. Pass in the
ARMMMUIdx, rather than the digested two_ranges boolean.
This is in preparation for FEAT_LPA2, where the interpretation
of 'value' depends on the effective value of DS for the regime.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/helper.c | 58 +++++++++++++++++++--------------------------
1 file changed, 24 insertions(+), 34 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 950f56599e..31c2a716f2 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -4511,70 +4511,60 @@ static void tlbi_aa64_vae3is_write(CPUARMState *env,
const ARMCPRegInfo *ri,
}
#ifdef TARGET_AARCH64
-static uint64_t tlbi_aa64_range_get_length(CPUARMState *env,
- uint64_t value)
-{
- unsigned int page_shift;
- unsigned int page_size_granule;
- uint64_t num;
- uint64_t scale;
- uint64_t exponent;
+typedef struct {
+ uint64_t base;
uint64_t length;
+} TLBIRange;
+
+static TLBIRange tlbi_aa64_get_range(CPUARMState *env, ARMMMUIdx mmuidx,
+ uint64_t value)
+{
+ unsigned int page_size_granule, page_shift, num, scale, exponent;
+ TLBIRange ret = { };
- num = extract64(value, 39, 5);
- scale = extract64(value, 44, 2);
page_size_granule = extract64(value, 46, 2);
if (page_size_granule == 0) {
qemu_log_mask(LOG_GUEST_ERROR, "Invalid page size granule %d\n",
page_size_granule);
- return 0;
+ return ret;
}
page_shift = (page_size_granule - 1) * 2 + 12;
-
+ num = extract64(value, 39, 5);
+ scale = extract64(value, 44, 2);
exponent = (5 * scale) + 1;
- length = (num + 1) << (exponent + page_shift);
- return length;
-}
+ ret.length = (num + 1) << (exponent + page_shift);
-static uint64_t tlbi_aa64_range_get_base(CPUARMState *env, uint64_t value,
- bool two_ranges)
-{
- /* TODO: ARMv8.7 FEAT_LPA2 */
- uint64_t pageaddr;
-
- if (two_ranges) {
- pageaddr = sextract64(value, 0, 37) << TARGET_PAGE_BITS;
+ if (regime_has_2_ranges(mmuidx)) {
+ ret.base = sextract64(value, 0, 37) << TARGET_PAGE_BITS;
} else {
- pageaddr = extract64(value, 0, 37) << TARGET_PAGE_BITS;
+ ret.base = extract64(value, 0, 37) << TARGET_PAGE_BITS;
}
- return pageaddr;
+ return ret;
}
static void do_rvae_write(CPUARMState *env, uint64_t value,
int idxmap, bool synced)
{
ARMMMUIdx one_idx = ARM_MMU_IDX_A | ctz32(idxmap);
- bool two_ranges = regime_has_2_ranges(one_idx);
- uint64_t baseaddr, length;
+ TLBIRange range;
int bits;
- baseaddr = tlbi_aa64_range_get_base(env, value, two_ranges);
- length = tlbi_aa64_range_get_length(env, value);
- bits = tlbbits_for_regime(env, one_idx, baseaddr);
+ range = tlbi_aa64_get_range(env, one_idx, value);
+ bits = tlbbits_for_regime(env, one_idx, range.base);
if (synced) {
tlb_flush_range_by_mmuidx_all_cpus_synced(env_cpu(env),
- baseaddr,
- length,
+ range.base,
+ range.length,
idxmap,
bits);
} else {
- tlb_flush_range_by_mmuidx(env_cpu(env), baseaddr,
- length, idxmap, bits);
+ tlb_flush_range_by_mmuidx(env_cpu(env), range.base,
+ range.length, idxmap, bits);
}
}
--
2.25.1
- [PATCH v3 00/17] target/arm: Implement LVA, LPA, LPA2 features, Richard Henderson, 2022/02/23
- [PATCH v3 01/17] hw/registerfields: Add FIELD_SEX<N> and FIELD_SDP<N>, Richard Henderson, 2022/02/23
- [PATCH v3 02/17] target/arm: Set TCR_EL1.TSZ for user-only, Richard Henderson, 2022/02/23
- [PATCH v3 03/17] target/arm: Fault on invalid TCR_ELx.TxSZ, Richard Henderson, 2022/02/23
- [PATCH v3 04/17] target/arm: Move arm_pamax out of line, Richard Henderson, 2022/02/23
- [PATCH v3 05/17] target/arm: Pass outputsize down to check_s2_mmu_setup, Richard Henderson, 2022/02/23
- [PATCH v3 06/17] target/arm: Use MAKE_64BIT_MASK to compute indexmask, Richard Henderson, 2022/02/23
- [PATCH v3 07/17] target/arm: Honor TCR_ELx.{I}PS, Richard Henderson, 2022/02/23
- [PATCH v3 08/17] target/arm: Prepare DBGBVR and DBGWVR for FEAT_LVA, Richard Henderson, 2022/02/23
- [PATCH v3 12/17] target/arm: Introduce tlbi_aa64_get_range,
Richard Henderson <=
- [PATCH v3 09/17] target/arm: Implement FEAT_LVA, Richard Henderson, 2022/02/23
- [PATCH v3 10/17] target/arm: Implement FEAT_LPA, Richard Henderson, 2022/02/23
- [PATCH v3 14/17] target/arm: Validate tlbi TG matches translation granule in use, Richard Henderson, 2022/02/23
- [PATCH v3 11/17] target/arm: Extend arm_fi_to_lfsc to level -1, Richard Henderson, 2022/02/23
- [PATCH v3 13/17] target/arm: Fix TLBIRange.base for 16k and 64k pages, Richard Henderson, 2022/02/23
- [PATCH v3 15/17] target/arm: Advertise all page sizes for -cpu max, Richard Henderson, 2022/02/23
- [PATCH v3 16/17] tests/avocado: Limit test_virt_tcg_gicv[23] to cortex-a72, Richard Henderson, 2022/02/23
- [PATCH v3 17/17] target/arm: Implement FEAT_LPA2, Richard Henderson, 2022/02/23