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[PATCH v2 10/15] target/arm: Implement FEAT_LPA
From: |
Richard Henderson |
Subject: |
[PATCH v2 10/15] target/arm: Implement FEAT_LPA |
Date: |
Thu, 10 Feb 2022 15:04:18 +1100 |
This feature widens physical addresses (and intermediate physical
addresses for 2-stage translation) from 48 to 52 bits, when using
64k pages. The only thing left at this point is to handle the
extra bits in the TTBR and in the table descriptors.
Note that PAR_EL1 and HPFAR_EL2 are nominally extended, but we don't
mask out the high bits when writing to those registers, so no changes
are required there.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/cpu-param.h | 2 +-
target/arm/cpu64.c | 2 +-
target/arm/helper.c | 19 ++++++++++++++++---
3 files changed, 18 insertions(+), 5 deletions(-)
diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h
index 5f9c288b1a..b59d505761 100644
--- a/target/arm/cpu-param.h
+++ b/target/arm/cpu-param.h
@@ -10,7 +10,7 @@
#ifdef TARGET_AARCH64
# define TARGET_LONG_BITS 64
-# define TARGET_PHYS_ADDR_SPACE_BITS 48
+# define TARGET_PHYS_ADDR_SPACE_BITS 52
# define TARGET_VIRT_ADDR_SPACE_BITS 52
#else
# define TARGET_LONG_BITS 32
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index d80a7eafac..707ae7767f 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -765,7 +765,7 @@ static void aarch64_max_initfn(Object *obj)
cpu->isar.id_aa64pfr1 = t;
t = cpu->isar.id_aa64mmfr0;
- t = FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 5); /* PARange: 48 bits */
+ t = FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 6); /* FEAT_LPA: 52 bits */
cpu->isar.id_aa64mmfr0 = t;
t = cpu->isar.id_aa64mmfr1;
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 62935b06d0..9b1b1b2611 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -11171,6 +11171,7 @@ static const uint8_t pamax_map[] = {
[3] = 42,
[4] = 44,
[5] = 48,
+ [6] = 52,
};
/* The cpu-specific constant value of PAMax; also used by hw/arm/virt. */
@@ -11562,11 +11563,15 @@ static bool get_phys_addr_lpae(CPUARMState *env,
uint64_t address,
descaddr = extract64(ttbr, 0, 48);
/*
- * If the base address is out of range, raise AddressSizeFault.
+ * For FEAT_LPA and PS=6, bits [51:48] of descaddr are in [5:2] of TTBR.
+ *
+ * Otherwise, if the base address is out of range, raise AddressSizeFault.
* In the pseudocode, this is !IsZero(baseregister<47:outputsize>),
* but we've just cleared the bits above 47, so simplify the test.
*/
- if (descaddr >> outputsize) {
+ if (outputsize > 48) {
+ descaddr |= extract64(ttbr, 2, 4) << 48;
+ } else if (descaddr >> outputsize) {
level = 0;
fault_type = ARMFault_AddressSize;
goto do_fault;
@@ -11618,7 +11623,15 @@ static bool get_phys_addr_lpae(CPUARMState *env,
uint64_t address,
}
descaddr = descriptor & descaddrmask;
- if (descaddr >> outputsize) {
+
+ /*
+ * For FEAT_LPA and PS=6, bits [51:48] of descaddr are in [15:12]
+ * of descriptor. Otherwise, if descaddr is out of range, raise
+ * AddressSizeFault.
+ */
+ if (outputsize > 48) {
+ descaddr |= extract64(descriptor, 12, 4) << 48;
+ } else if (descaddr >> outputsize) {
fault_type = ARMFault_AddressSize;
goto do_fault;
}
--
2.25.1
- [PATCH v2 07/15] target/arm: Honor TCR_ELx.{I}PS, (continued)
- [PATCH v2 07/15] target/arm: Honor TCR_ELx.{I}PS, Richard Henderson, 2022/02/09
- [PATCH v2 08/15] target/arm: Prepare DBGBVR and DBGWVR for FEAT_LVA, Richard Henderson, 2022/02/09
- [PATCH v2 09/15] target/arm: Implement FEAT_LVA, Richard Henderson, 2022/02/09
- [PATCH v2 11/15] target/arm: Extend arm_fi_to_lfsc to level -1, Richard Henderson, 2022/02/09
- [PATCH v2 14/15] target/arm: Validate tlbi TG matches translation granule in use, Richard Henderson, 2022/02/09
- [PATCH v2 10/15] target/arm: Implement FEAT_LPA,
Richard Henderson <=
- [PATCH v2 13/15] target/arm: Fix TLBIRange.base for 16k and 64k pages, Richard Henderson, 2022/02/09
- [PATCH v2 15/15] target/arm: Implement FEAT_LPA2, Richard Henderson, 2022/02/09
- [PATCH v2 12/15] target/arm: Introduce tlbi_aa64_get_range, Richard Henderson, 2022/02/09
- Re: [PATCH v2 00/15] target/arm: Implement LVA, LPA, LPA2 features, Peter Maydell, 2022/02/16
- Re: [PATCH v2 00/15] target/arm: Implement LVA, LPA, LPA2 features, Peter Maydell, 2022/02/17