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[PATCH 14/16] hw/arm/highbank: Drop unused secondary boot stub code
From: |
Peter Maydell |
Subject: |
[PATCH 14/16] hw/arm/highbank: Drop unused secondary boot stub code |
Date: |
Thu, 27 Jan 2022 15:46:37 +0000 |
The highbank and midway board code includes boot-stub code for
handling secondary CPU boot which keeps the secondaries in a pen
until the primary writes to a known location with the address they
should jump to.
This code is never used, because the boards enable QEMU's PSCI
emulation, so secondary CPUs are kept powered off until the PSCI call
which turns them on, and then start execution from the address given
by the guest in that PSCI call. Delete the unreachable code.
(The code was wrong for midway in any case -- on the Cortex-A15 the
GIC CPU interface registers are at a different offset from PERIPHBASE
compared to the Cortex-A9, and the code baked-in the offsets for
highbank's A9.)
Note that this commit implicitly depends on the preceding "Don't
write secondary boot stub if using PSCI" commit -- the default
secondary-boot stub code overlaps with one of the highbank-specific
bootcode rom blobs, so we must suppress the secondary-boot
stub code entirely, not merely replace the highbank-specific
version with the default.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/highbank.c | 56 -----------------------------------------------
1 file changed, 56 deletions(-)
diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c
index a21afd178d1..da681b15708 100644
--- a/hw/arm/highbank.c
+++ b/hw/arm/highbank.c
@@ -48,60 +48,6 @@
/* Board init. */
-static void hb_write_secondary(ARMCPU *cpu, const struct arm_boot_info *info)
-{
- int n;
- uint32_t smpboot[] = {
- 0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 - read current core id */
- 0xe210000f, /* ands r0, r0, #0x0f */
- 0xe3a03040, /* mov r3, #0x40 - jump address is 0x40 + 0x10 * core id */
- 0xe0830200, /* add r0, r3, r0, lsl #4 */
- 0xe59f2024, /* ldr r2, privbase */
- 0xe3a01001, /* mov r1, #1 */
- 0xe5821100, /* str r1, [r2, #256] - set GICC_CTLR.Enable */
- 0xe3a010ff, /* mov r1, #0xff */
- 0xe5821104, /* str r1, [r2, #260] - set GICC_PMR.Priority to 0xff */
- 0xf57ff04f, /* dsb */
- 0xe320f003, /* wfi */
- 0xe5901000, /* ldr r1, [r0] */
- 0xe1110001, /* tst r1, r1 */
- 0x0afffffb, /* beq <wfi> */
- 0xe12fff11, /* bx r1 */
- MPCORE_PERIPHBASE /* privbase: MPCore peripheral base address. */
- };
- for (n = 0; n < ARRAY_SIZE(smpboot); n++) {
- smpboot[n] = tswap32(smpboot[n]);
- }
- rom_add_blob_fixed_as("smpboot", smpboot, sizeof(smpboot), SMP_BOOT_ADDR,
- arm_boot_address_space(cpu, info));
-}
-
-static void hb_reset_secondary(ARMCPU *cpu, const struct arm_boot_info *info)
-{
- CPUARMState *env = &cpu->env;
-
- switch (info->nb_cpus) {
- case 4:
- address_space_stl_notdirty(&address_space_memory,
- SMP_BOOT_REG + 0x30, 0,
- MEMTXATTRS_UNSPECIFIED, NULL);
- /* fallthrough */
- case 3:
- address_space_stl_notdirty(&address_space_memory,
- SMP_BOOT_REG + 0x20, 0,
- MEMTXATTRS_UNSPECIFIED, NULL);
- /* fallthrough */
- case 2:
- address_space_stl_notdirty(&address_space_memory,
- SMP_BOOT_REG + 0x10, 0,
- MEMTXATTRS_UNSPECIFIED, NULL);
- env->regs[15] = SMP_BOOT_ADDR;
- break;
- default:
- break;
- }
-}
-
#define NUM_REGS 0x200
static void hb_regs_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
@@ -380,8 +326,6 @@ static void calxeda_init(MachineState *machine, enum
cxmachines machine_id)
highbank_binfo.board_id = -1;
highbank_binfo.nb_cpus = smp_cpus;
highbank_binfo.loader_start = 0;
- highbank_binfo.write_secondary_boot = hb_write_secondary;
- highbank_binfo.secondary_cpu_reset_hook = hb_reset_secondary;
highbank_binfo.board_setup_addr = BOARD_SETUP_ADDR;
highbank_binfo.psci_conduit = QEMU_PSCI_CONDUIT_SMC;
--
2.25.1
- [PATCH 05/16] hw/arm: allwinner: Don't enable PSCI conduit when booting guest in EL3, (continued)
- [PATCH 05/16] hw/arm: allwinner: Don't enable PSCI conduit when booting guest in EL3, Peter Maydell, 2022/01/27
- [PATCH 06/16] hw/arm/xlnx-zcu102: Don't enable PSCI conduit when booting guest in EL3, Peter Maydell, 2022/01/27
- [PATCH 07/16] hw/arm/versal: Let boot.c handle PSCI enablement, Peter Maydell, 2022/01/27
- [PATCH 08/16] hw/arm/virt: Let boot.c handle PSCI enablement, Peter Maydell, 2022/01/27
- [PATCH 09/16] hw/arm: highbank: For EL3 guests, don't enable PSCI, start all cores, Peter Maydell, 2022/01/27
- [PATCH 14/16] hw/arm/highbank: Drop unused secondary boot stub code,
Peter Maydell <=
- [PATCH 10/16] Revert "Revert "arm: tcg: Adhere to SMCCC 1.3 section 5.2"", Peter Maydell, 2022/01/27
- [PATCH 13/16] hw/arm/boot: Don't write secondary boot stub if using PSCI, Peter Maydell, 2022/01/27
- [PATCH 11/16] hw/arm/highbank: Drop use of secure_board_setup, Peter Maydell, 2022/01/27
- [PATCH 15/16] hw/arm/boot: Drop nb_cpus field from arm_boot_info, Peter Maydell, 2022/01/27
- [PATCH 12/16] hw/arm/boot: Prevent setting both psci_conduit and secure_board_setup, Peter Maydell, 2022/01/27