Re: [PATCH] target/arm: Allow only specific instructions based on the SCTLR_EL1.UCI bit

[Peter Maydell]

On Fri, 14 Jan 2022 at 00:40, Idan Horowitz <idan.horowitz@gmail.com> wrote:
>
> The SCTLR_EL1.UCI bit only affects a subset of cache maintenance
> instructions as specified by the specification. Any other cache
> maintenance instructions must still be trapped from EL0.

Hi; thanks for this patch. Do you have a test case which
demonstrates this behaviour? From reading the patch I
can't see any instructions where the patch changes the
behaviour of the emulation.

As far as I can see, the commit effectively changes the
accessfn for the following instructions to one which does
not check the UCI bit:
AArch64
 IC IALLUIS
 IC IALLU
 DC IVAC
 DC IGVAC
 DC IGDVAC
AArch32
 ICIALLUIS
 ICIALLU
 ICIMVAU
 DCCMVAU
 DCIMVAC
 DCCMVAC
 DCCIMVAC

and it is true that the architecture says that UCI
doesn't affect these instructions; they always UNDEF at EL0.

But for all of these instructions the reginfo struct
sets ".access = PL1_W". The .access field is always
checked before the .accessfn, so for any of these instructions
executed from EL0 I think we will always fail the .access
check and UNDEF the insn without calling the .accessfn.
So it doesn't matter that the .accessfn has "if EL0 then
check SCTLR_EL1.UCI", because when running the accessfn
for these insns we can never be in EL0.

Am I missing something?

thanks
-- PMM