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Re: [PATCH] Target/arm: Implement Cortex-A5

From: Byron Lathi
Subject: Re: [PATCH] Target/arm: Implement Cortex-A5
Date: Mon, 13 Dec 2021 16:34:14 -0600

The goal for me was to eventually add the SAMA5D, so I might have made some assumptions that were not correct for all devices. My apologies for the typos.
I will add those changes and re-submit.

On Mon, Dec 13, 2021 at 3:46 PM Richard Henderson <richard.henderson@linaro.org> wrote:
On 12/13/21 1:02 PM, Alex Bennée wrote:
>> +    cpu->midr = 0x410fc0f1;
> hmm wikipedia lists the part number as 0xc05 (and the a15 as 0xc0f) but
> I can't find the actual value in the TRM.


has exactly this value at the top of table 4-9.

>> +    cpu->reset_fpsid = 0x41023051;
> I think for the a5 the FPU is optional so maybe we need a cpu option
> here? Or maybe just assume it's enabled on QEMUs version?

Yeah, there's no entry for fpsid in the above manual.

>> +    cpu->isar.id_mmfr0 = 0x00100103;
> the TRM says [11:8] Outermost shareability 0x0 L1 cache coherency not supported.

Again, this does match table 4-9.


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