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Re: [PATCH v2 for 6.2?] gicv3: fix ICH_MISR's LRENP computation

From: Damien Hedde
Subject: Re: [PATCH v2 for 6.2?] gicv3: fix ICH_MISR's LRENP computation
Date: Tue, 7 Dec 2021 14:05:12 +0100
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.3.2

On 12/7/21 13:45, Philippe Mathieu-Daudé wrote:
On 12/7/21 10:44, Damien Hedde wrote:
According to the "Arm Generic Interrupt Controller Architecture
Specification GIC architecture version 3 and 4" (version G: page 345
for aarch64 or 509 for aarch32):
LRENP bit of ICH_MISR is set when ICH_HCR.LRENPIE==1 and
ICH_HCR.EOIcount is non-zero.

When only LRENPIE was set (and EOI count was zero), the LRENP bit was
wrongly set and MISR value was wrong.

As an additional consequence, if an hypervisor set ICH_HCR.LRENPIE,
the maintenance interrupt was constantly fired. It happens since patch
9cee1efe92 ("hw/intc: Set GIC maintenance interrupt level to only 0 or 1")
which fixed another bug about maintenance interrupt (most significant
bits of misr, including this one, were ignored in the interrupt trigger).

Fixes: 83f036fe3d ("hw/intc/arm_gicv3: Add accessors for ICH_ system registers")

This commit predates 6.1 release, so technically this is not
a regression for 6.2.

Do you mean "Fixes:" is meant only for regression or simply that this patch should not go for 6.2 ?

9cee1efe92 was introduced after 6.1, and changed the interrupt behavior. Thought I'm not sure if we can consider this as a fix for 9cee1efe92: it only makes the previous error more visible.


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