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Re: [PATCH v2 10/18] target/arm: Implement MVE FP max/min across vector
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From: |
Peter Maydell |
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Subject: |
Re: [PATCH v2 10/18] target/arm: Implement MVE FP max/min across vector |
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Date: |
Mon, 30 Aug 2021 10:17:18 +0100 |
On Thu, 26 Aug 2021 at 14:17, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> Implement the MVE VMAXNMV, VMINNMV, VMAXNMAV, VMINNMAV insns. These
> calculate the maximum or minimum of floating point elements across a
> vector, starting with a value in a general purpose register and
> returning the result there.
>
> @@ -440,6 +444,10 @@ VMLADAV_S 1110 1110 1111 ... 0 ... . 1111 . 0 .
> 0 ... 1 @vmladav_nosz
> VMLADAV_U 1111 1110 1111 ... 0 ... . 1111 . 0 . 0 ... 1 @vmladav_nosz
>
> {
> + VMAXNMAV 1110 1110 1110 11 00 .... 1111 0 0 . 0 ... 0 @vmaxnmv
> size=2
> + VMINNMAV 1110 1110 1110 11 00 .... 1111 1 0 . 0 ... 0 @vmaxnmv
> size=2
> + VMAXNMV 1110 1110 1110 11 10 .... 1111 0 0 . 0 ... 0 @vmaxnmv
> size=2
> + VMINNMV 1110 1110 1110 11 10 .... 1111 1 0 . 0 ... 0 @vmaxnmv
> size=2
> VMAXV_S 1110 1110 1110 .. 10 .... 1111 0 0 . 0 ... 0 @vmaxv
> VMINV_S 1110 1110 1110 .. 10 .... 1111 1 0 . 0 ... 0 @vmaxv
> VMAXAV 1110 1110 1110 .. 00 .... 1111 0 0 . 0 ... 0 @vmaxv
> @@ -449,6 +457,10 @@ VMLADAV_U 1111 1110 1111 ... 0 ... . 1111 . 0 .
> 0 ... 1 @vmladav_nosz
> }
>
> {
> + VMAXNMAV 1111 1110 1110 11 00 .... 1111 0 0 . 0 ... 0 @vmaxnmv
> size=1
> + VMINNMAV 1111 1110 1110 11 00 .... 1111 1 0 . 0 ... 0 @vmaxnmv
> size=1
> + VMAXNMV 1111 1110 1110 11 10 .... 1111 0 0 . 0 ... 0 @vmaxnmv
> size=1
> + VMINNMV 1111 1110 1110 11 10 .... 1111 1 0 . 0 ... 0 @vmaxnmv
> size=1
> VMAXV_U 1111 1110 1110 .. 10 .... 1111 0 0 . 0 ... 0 @vmaxv
> VMINV_U 1111 1110 1110 .. 10 .... 1111 1 0 . 0 ... 0 @vmaxv
> VMLADAV_U 1111 1110 1111 ... 0 ... . 1111 . 0 . 0 ... 0 @vmladav_nosz
I just realized that I forgot to do part of Richard's review
comments on the first version of this patch, about adding some
extra [] blocks here.
https://patchew.org/QEMU/20210729111512.16541-1-peter.maydell@linaro.org/20210729111512.16541-46-peter.maydell@linaro.org/
Diff to squash in:
index 1a18c3b8eeb..a46372f8c77 100644
--- a/target/arm/mve.decode
+++ b/target/arm/mve.decode
@@ -444,25 +444,33 @@ VMLADAV_S 1110 1110 1111 ... 0 ... .
1111 . 0 . 0 ... 1 @vmladav_nosz
VMLADAV_U 1111 1110 1111 ... 0 ... . 1111 . 0 . 0 ... 1 @vmladav_nosz
{
- VMAXNMAV 1110 1110 1110 11 00 .... 1111 0 0 . 0 ... 0 @vmaxnmv size=2
- VMINNMAV 1110 1110 1110 11 00 .... 1111 1 0 . 0 ... 0 @vmaxnmv size=2
- VMAXNMV 1110 1110 1110 11 10 .... 1111 0 0 . 0 ... 0 @vmaxnmv size=2
- VMINNMV 1110 1110 1110 11 10 .... 1111 1 0 . 0 ... 0 @vmaxnmv size=2
- VMAXV_S 1110 1110 1110 .. 10 .... 1111 0 0 . 0 ... 0 @vmaxv
- VMINV_S 1110 1110 1110 .. 10 .... 1111 1 0 . 0 ... 0 @vmaxv
- VMAXAV 1110 1110 1110 .. 00 .... 1111 0 0 . 0 ... 0 @vmaxv
- VMINAV 1110 1110 1110 .. 00 .... 1111 1 0 . 0 ... 0 @vmaxv
+ [
+ VMAXNMAV 1110 1110 1110 11 00 .... 1111 0 0 . 0 ... 0 @vmaxnmv size=2
+ VMINNMAV 1110 1110 1110 11 00 .... 1111 1 0 . 0 ... 0 @vmaxnmv size=2
+ VMAXNMV 1110 1110 1110 11 10 .... 1111 0 0 . 0 ... 0 @vmaxnmv size=2
+ VMINNMV 1110 1110 1110 11 10 .... 1111 1 0 . 0 ... 0 @vmaxnmv size=2
+ ]
+ [
+ VMAXV_S 1110 1110 1110 .. 10 .... 1111 0 0 . 0 ... 0 @vmaxv
+ VMINV_S 1110 1110 1110 .. 10 .... 1111 1 0 . 0 ... 0 @vmaxv
+ VMAXAV 1110 1110 1110 .. 00 .... 1111 0 0 . 0 ... 0 @vmaxv
+ VMINAV 1110 1110 1110 .. 00 .... 1111 1 0 . 0 ... 0 @vmaxv
+ ]
VMLADAV_S 1110 1110 1111 ... 0 ... . 1111 . 0 . 0 ... 0 @vmladav_nosz
VRMLALDAVH_S 1110 1110 1 ... ... 0 ... . 1111 . 0 . 0 ... 0 @vmlaldav_nosz
}
{
- VMAXNMAV 1111 1110 1110 11 00 .... 1111 0 0 . 0 ... 0 @vmaxnmv size=1
- VMINNMAV 1111 1110 1110 11 00 .... 1111 1 0 . 0 ... 0 @vmaxnmv size=1
- VMAXNMV 1111 1110 1110 11 10 .... 1111 0 0 . 0 ... 0 @vmaxnmv size=1
- VMINNMV 1111 1110 1110 11 10 .... 1111 1 0 . 0 ... 0 @vmaxnmv size=1
- VMAXV_U 1111 1110 1110 .. 10 .... 1111 0 0 . 0 ... 0 @vmaxv
- VMINV_U 1111 1110 1110 .. 10 .... 1111 1 0 . 0 ... 0 @vmaxv
+ [
+ VMAXNMAV 1111 1110 1110 11 00 .... 1111 0 0 . 0 ... 0 @vmaxnmv size=1
+ VMINNMAV 1111 1110 1110 11 00 .... 1111 1 0 . 0 ... 0 @vmaxnmv size=1
+ VMAXNMV 1111 1110 1110 11 10 .... 1111 0 0 . 0 ... 0 @vmaxnmv size=1
+ VMINNMV 1111 1110 1110 11 10 .... 1111 1 0 . 0 ... 0 @vmaxnmv size=1
+ ]
+ [
+ VMAXV_U 1111 1110 1110 .. 10 .... 1111 0 0 . 0 ... 0 @vmaxv
+ VMINV_U 1111 1110 1110 .. 10 .... 1111 1 0 . 0 ... 0 @vmaxv
+ ]
VMLADAV_U 1111 1110 1111 ... 0 ... . 1111 . 0 . 0 ... 0 @vmladav_nosz
VRMLALDAVH_U 1111 1110 1 ... ... 0 ... . 1111 . 0 . 0 ... 0 @vmlaldav_nosz
}
-- PMM
- [PATCH v2 03/18] target/arm: Implement MVE VCADD, (continued)
- [PATCH v2 03/18] target/arm: Implement MVE VCADD, Peter Maydell, 2021/08/26
- [PATCH v2 08/18] target/arm: Implement MVE fp-with-scalar VFMA, VFMAS, Peter Maydell, 2021/08/26
- [PATCH v2 12/18] target/arm: Implement MVE fp scalar comparisons, Peter Maydell, 2021/08/26
- [PATCH v2 04/18] target/arm: Implement MVE VFMA and VFMS, Peter Maydell, 2021/08/26
- [PATCH v2 09/18] softfloat: Remove assertion preventing silencing of NaN in default-NaN mode, Peter Maydell, 2021/08/26
- [PATCH v2 13/18] target/arm: Implement MVE VCVT between floating and fixed point, Peter Maydell, 2021/08/26
- [PATCH v2 16/18] target/arm: Implement MVE VCVT between single and half precision, Peter Maydell, 2021/08/26
- [PATCH v2 14/18] target/arm: Implement MVE VCVT between fp and integer, Peter Maydell, 2021/08/26
- [PATCH v2 11/18] target/arm: Implement MVE fp vector comparisons, Peter Maydell, 2021/08/26
- [PATCH v2 10/18] target/arm: Implement MVE FP max/min across vector, Peter Maydell, 2021/08/26
- Re: [PATCH v2 10/18] target/arm: Implement MVE FP max/min across vector,
Peter Maydell <=
- [PATCH v2 15/18] target/arm: Implement MVE VCVT with specified rounding mode, Peter Maydell, 2021/08/26
- [PATCH v2 18/18] target/arm: Enable MVE in Cortex-M55, Peter Maydell, 2021/08/26
- [PATCH v2 17/18] target/arm: Implement MVE VRINT insns, Peter Maydell, 2021/08/26