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Re: [PATCH for-6.2 08/25] hw/arm/mps2.c: Connect up armv7m clocks
From: |
Luc Michel |
Subject: |
Re: [PATCH for-6.2 08/25] hw/arm/mps2.c: Connect up armv7m clocks |
Date: |
Tue, 17 Aug 2021 11:39:18 +0200 |
On 10:33 Thu 12 Aug , Peter Maydell wrote:
> Connect up the armv7m clocks on the mps2-an385/386/500/511.
>
> Connect up the armv7m object's clocks on the MPS boards defined in
> mps2.c. The documentation for these FPGA images doesn't specify what
> systick reference clock is used (if any), so for the moment we
> provide a 1MHz refclock, which will result in no behavioural change
> from the current hardwired 1MHz clock implemented in
> armv7m_systick.c:systick_scale().
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Luc Michel <luc@lmichel.fr>
> ---
> hw/arm/mps2.c | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
>
> diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
> index 81413b7133e..3671f49ad7b 100644
> --- a/hw/arm/mps2.c
> +++ b/hw/arm/mps2.c
> @@ -86,6 +86,7 @@ struct MPS2MachineState {
> CMSDKAPBWatchdog watchdog;
> CMSDKAPBTimer timer[2];
> Clock *sysclk;
> + Clock *refclk;
> };
>
> #define TYPE_MPS2_MACHINE "mps2"
> @@ -99,6 +100,15 @@ OBJECT_DECLARE_TYPE(MPS2MachineState, MPS2MachineClass,
> MPS2_MACHINE)
> /* Main SYSCLK frequency in Hz */
> #define SYSCLK_FRQ 25000000
>
> +/*
> + * The Application Notes don't say anything about how the
> + * systick reference clock is configured. (Quite possibly
> + * they don't have one at all.) This 1MHz clock matches the
> + * pre-existing behaviour that used to be hardcoded in the
> + * armv7m_systick implementation.
> + */
> +#define REFCLK_FRQ (1 * 1000 * 1000)
> +
> /* Initialize the auxiliary RAM region @mr and map it into
> * the memory map at @base.
> */
> @@ -146,6 +156,9 @@ static void mps2_common_init(MachineState *machine)
> mms->sysclk = clock_new(OBJECT(machine), "SYSCLK");
> clock_set_hz(mms->sysclk, SYSCLK_FRQ);
>
> + mms->refclk = clock_new(OBJECT(machine), "REFCLK");
> + clock_set_hz(mms->refclk, REFCLK_FRQ);
> +
> /* The FPGA images have an odd combination of different RAMs,
> * because in hardware they are different implementations and
> * connected to different buses, giving varying performance/size
> @@ -223,6 +236,8 @@ static void mps2_common_init(MachineState *machine)
> default:
> g_assert_not_reached();
> }
> + qdev_connect_clock_in(armv7m, "cpuclk", mms->sysclk);
> + qdev_connect_clock_in(armv7m, "refclk", mms->refclk);
> qdev_prop_set_string(armv7m, "cpu-type", machine->cpu_type);
> qdev_prop_set_bit(armv7m, "enable-bitband", true);
> object_property_set_link(OBJECT(&mms->armv7m), "memory",
> --
> 2.20.1
>
--
- [PATCH for-6.2 03/25] arm: Move system PPB container handling to armv7m, (continued)
- [PATCH for-6.2 03/25] arm: Move system PPB container handling to armv7m, Peter Maydell, 2021/08/12
- [PATCH for-6.2 07/25] armsse: Wire up systick cpuclk clock, Peter Maydell, 2021/08/12
- [PATCH for-6.2 05/25] hw/timer/armv7m_systick: Add input clocks, Peter Maydell, 2021/08/12
- [PATCH for-6.2 08/25] hw/arm/mps2.c: Connect up armv7m clocks, Peter Maydell, 2021/08/12
- Re: [PATCH for-6.2 08/25] hw/arm/mps2.c: Connect up armv7m clocks,
Luc Michel <=
- [PATCH for-6.2 06/25] hw/arm/armv7m: Create input clocks, Peter Maydell, 2021/08/12
- [PATCH for-6.2 09/25] clock: Provide builtin multiplier/divider, Peter Maydell, 2021/08/12