Re: [PATCH 0/2] arm: Implement M-profile trapping on division by zero

[Richard Henderson]

On 7/30/21 5:16 AM, Peter Maydell wrote:
> Unlike A-profile, for M-profile the UDIV and SDIV insns can be
> configured to raise an exception on division by zero, using the CCR
> DIV_0_TRP bit.  This patchset implements that missing functionality
> by having the udiv and sdiv helpers raise an exception if needed.
>
> Some questions:
>
> Is it worth allowing A-profile to retain the mildly better codegen it
> gets from not having to pass in 'env' and marking the helper as
> no-side-effects (ie having M-specific udiv/sdiv helpers) ?

Probably not.

> Is it worth inlining either udiv or sdiv for the A-profile case?

Probably not.

>    mov_i32 tmp3,r2
>    mov_i32 tmp6,r3
>    movcond_i32 tmp3,tmp6,$0x0,$0x0,tmp3,eq
>    movcond_i32 tmp6,tmp6,$0x0,$0x1,tmp6,eq
>    mov_i32 tmp7,$0x0
>    divu2_i32 tmp3,tmp7,tmp3,tmp7,tmp6
>    mov_i32 r3,tmp3
>
> but the x86 code is
> 0x7f5f1807dc0c:  45 33 f6                 xorl     %r14d, %r14d
> 0x7f5f1807dc0f:  45 85 ed                 testl    %r13d, %r13d
> 0x7f5f1807dc12:  45 0f 44 e6              cmovel   %r14d, %r12d


At the start of the first movcond, $0x0 is not allocated to a register, and the 
constraints allow a constant for argument 3.  Then, constraints do not allow a constant 
for argument 4 so we load $0x0 into a register.

> 0x7f5f1807dc16:  41 bf 01 00 00 00        movl     $1, %r15d
> 0x7f5f1807dc1c:  45 3b ee                 cmpl     %r14d, %r13d
> 0x7f5f1807dc1f:  45 0f 44 ef              cmovel   %r15d, %r13d

At the start of the second movcond, $0x0 is loaded into a register, so we use 
it.

> (Ideally of
> course it would notice that it already had generated the condition
> check and not repeat it.)

Yep.


r~