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[PATCH for-6.1 5/6] hw/intc/armv7m_nvic: Correct size of ICSR.VECTPENDIN
From: |
Peter Maydell |
Subject: |
[PATCH for-6.1 5/6] hw/intc/armv7m_nvic: Correct size of ICSR.VECTPENDING |
Date: |
Fri, 23 Jul 2021 17:21:45 +0100 |
The VECTPENDING field in the ICSR is 9 bits wide, in bits [20:12] of
the register. We were incorrectly masking it to 8 bits, so it would
report the wrong value if the pending exception was greater than 256.
Fix the bug.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/intc/armv7m_nvic.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index 2aba2136822..c9149a3b221 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -1039,7 +1039,7 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset,
MemTxAttrs attrs)
/* VECTACTIVE */
val = cpu->env.v7m.exception;
/* VECTPENDING */
- val |= (s->vectpending & 0xff) << 12;
+ val |= (s->vectpending & 0x1ff) << 12;
/* ISRPENDING - set if any external IRQ is pending */
if (nvic_isrpending(s)) {
val |= (1 << 22);
--
2.20.1
- [PATCH for-6.1 1/6] target/arm: Enforce that M-profile SP low 2 bits are always zero, (continued)
- [PATCH for-6.1 1/6] target/arm: Enforce that M-profile SP low 2 bits are always zero, Peter Maydell, 2021/07/23
- [PATCH for-6.1 3/6] target/arm: Report M-profile alignment faults correctly to the guest, Peter Maydell, 2021/07/23
- [PATCH for-6.1 2/6] target/arm: Add missing 'return's after calling v7m_exception_taken(), Peter Maydell, 2021/07/23
- [PATCH for-6.1 6/6] hw/intc/armv7m_nvic: for v8.1M VECTPENDING hides S exceptions from NS, Peter Maydell, 2021/07/23
- [PATCH for-6.1 4/6] hw/intc/armv7m_nvic: ISCR.ISRPENDING is set for non-enabled pending interrupts, Peter Maydell, 2021/07/23
- [PATCH for-6.1 5/6] hw/intc/armv7m_nvic: Correct size of ICSR.VECTPENDING,
Peter Maydell <=