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[PATCH for-6.2 00/34] target/arm: Third slice of MVE implementation
From: |
Peter Maydell |
Subject: |
[PATCH for-6.2 00/34] target/arm: Third slice of MVE implementation |
Date: |
Tue, 13 Jul 2021 14:36:52 +0100 |
This patchseries provides the third slice of the MVE implementation.
In this series:
* fixes for minor bugs in a couple of the insns already upstream
* all the remaining integer instructions
* the remaining loads and stores (scatter-gather and interleaving)
This is obviously for-6.2 material, so no urgency in reviewing it.
But "all the integer stuff done" seemed like an obvious natural
break point to send out what I've done so far.
I apologize in advance for the final patch, which was tricky for
me to write and is probably going to be painful to review too.
This is mostly because I find the interleaving loads/stores
rather confusing...
thanks
-- PMM
Peter Maydell (34):
target/arm: Note that we handle VMOVL as a special case of VSHLL
target/arm: Print MVE VPR in CPU dumps
target/arm: Fix MVE VSLI by 0 and VSRI by <dt>
target/arm: Fix signed VADDV
target/arm: Fix mask handling for MVE narrowing operations
target/arm: Fix 48-bit saturating shifts
target/arm: Fix calculation of LTP mask when LR is 0
target/arm: Fix VPT advance when ECI is non-zero
target/arm: Factor out mve_eci_mask()
target/arm: Fix VLDRB/H/W for predicated elements
target/arm: Implement MVE VMULL (polynomial)
target/arm: Implement MVE incrementing/decrementing dup insns
target/arm: Factor out gen_vpst()
target/arm: Implement MVE integer vector comparisons
target/arm: Implement MVE integer vector-vs-scalar comparisons
target/arm: Implement MVE VPSEL
target/arm: Implement MVE VMLAS
target/arm: Implement MVE shift-by-scalar
target/arm: Move 'x' and 'a' bit definitions into vmlaldav formats
target/arm: Implement MVE integer min/max across vector
target/arm: Implement MVE VABAV
target/arm: Implement MVE narrowing moves
target/arm: Rename MVEGenDualAccOpFn to MVEGenLongDualAccOpFn
target/arm: Implement MVE VMLADAV and VMLSLDAV
target/arm: Implement MVE VMLA
target/arm: Implement MVE saturating doubling multiply accumulates
target/arm: Implement MVE VQABS, VQNEG
target/arm: Implement MVE VMAXA, VMINA
target/arm: Implement MVE VMOV to/from 2 general-purpose registers
target/arm: Implement MVE VPNOT
target/arm: Implement MVE VCTP
target/arm: Implement MVE scatter-gather insns
target/arm: Implement MVE scatter-gather immediate forms
target/arm: Implement MVE interleaving loads/stores
target/arm/helper-mve.h | 295 +++++++++
target/arm/translate-a32.h | 2 +
target/arm/vec_internal.h | 11 +
target/arm/mve.decode | 228 ++++++-
target/arm/t32.decode | 1 +
target/arm/cpu.c | 3 +
target/arm/mve_helper.c | 1259 ++++++++++++++++++++++++++++++++++--
target/arm/translate-mve.c | 865 ++++++++++++++++++++++++-
target/arm/translate-vfp.c | 2 +-
target/arm/translate.c | 33 +
target/arm/vec_helper.c | 14 +-
11 files changed, 2628 insertions(+), 85 deletions(-)
--
2.20.1
- [PATCH for-6.2 00/34] target/arm: Third slice of MVE implementation,
Peter Maydell <=
- [PATCH for-6.2 01/34] target/arm: Note that we handle VMOVL as a special case of VSHLL, Peter Maydell, 2021/07/13
- [PATCH for-6.2 03/34] target/arm: Fix MVE VSLI by 0 and VSRI by <dt>, Peter Maydell, 2021/07/13
- [PATCH for-6.2 02/34] target/arm: Print MVE VPR in CPU dumps, Peter Maydell, 2021/07/13
- [PATCH for-6.2 04/34] target/arm: Fix signed VADDV, Peter Maydell, 2021/07/13
- [PATCH for-6.2 06/34] target/arm: Fix 48-bit saturating shifts, Peter Maydell, 2021/07/13