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Re: [PATCH 1/2] arm/virt: fix irq mapping for gpio_pwr
From: |
Maxim Uvarov |
Subject: |
Re: [PATCH 1/2] arm/virt: fix irq mapping for gpio_pwr |
Date: |
Fri, 25 Jun 2021 17:03:33 +0300 |
On Fri, 25 Jun 2021 at 14:58, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> On Fri, 25 Jun 2021 at 12:18, Maxim Uvarov <maxim.uvarov@linaro.org> wrote:
> >
> > Fix irq mapping for virt machine reboot and shutdown
> > interrupts triggered from ATF code.
> >
> > Signed-off-by: Maxim Uvarov <maxim.uvarov@linaro.org>
> > ---
> > hw/arm/virt.c | 4 ++--
> > 1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/hw/arm/virt.c b/hw/arm/virt.c
> > index 4b96f06014..d83f4ebdd3 100644
> > --- a/hw/arm/virt.c
> > +++ b/hw/arm/virt.c
> > @@ -846,8 +846,8 @@ static void create_gpio_keys(char *fdt, DeviceState
> > *pl061_dev,
> > "gpios", phandle, 3, 0);
> > }
> >
> > -#define SECURE_GPIO_POWEROFF 0
> > -#define SECURE_GPIO_RESET 1
> > +#define SECURE_GPIO_POWEROFF 1
> > +#define SECURE_GPIO_RESET 2
>
> I don't understand why this is needed. QEMU counts its GPIO
> lines from 0 for the PL061, so wiring up lines 1 and 2
> should be no different from using lines 0 and 1 (either way,
> we tell the guest what lines to use in the device tree).
>
> -- PMM
For now we do not tell in the device tree. It's pin 0 for poweroff and
pin 1 for reboot;
https://github.com/ARM-software/arm-trusted-firmware/blob/master/plat/qemu/qemu/include/platform_def.h#L94
https://github.com/ARM-software/arm-trusted-firmware/blob/master/plat/qemu/common/qemu_pm.c#L211
But to answer the question why 0 and 1 do not work and 1 and 2 works I
need to do some debugging on pl061 or qemu interrupt code.
Regards,
Maxim.