[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [PATCH v3 35/44] target/arm: Implmement MVE VRSHL
From: |
Claudio Fontana |
Subject: |
Re: [PATCH v3 35/44] target/arm: Implmement MVE VRSHL |
Date: |
Thu, 17 Jun 2021 15:20:51 +0200 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.12.0 |
Hi, typo in the Subject: "Implmement MVE VRSHL"
Claudio
On 6/17/21 2:16 PM, Peter Maydell wrote:
> Implement the MVE VRSHL insn (vector form).
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/arm/helper-mve.h | 8 ++++++++
> target/arm/mve.decode | 3 +++
> target/arm/mve_helper.c | 4 ++++
> target/arm/translate-mve.c | 2 ++
> 4 files changed, 17 insertions(+)
>
> diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
> index 56b3e8591ad..b7e2243a19a 100644
> --- a/target/arm/helper-mve.h
> +++ b/target/arm/helper-mve.h
> @@ -177,6 +177,14 @@ DEF_HELPER_FLAGS_4(mve_vshlub, TCG_CALL_NO_WG, void,
> env, ptr, ptr, ptr)
> DEF_HELPER_FLAGS_4(mve_vshluh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
> DEF_HELPER_FLAGS_4(mve_vshluw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
>
> +DEF_HELPER_FLAGS_4(mve_vrshlsb, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
> +DEF_HELPER_FLAGS_4(mve_vrshlsh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
> +DEF_HELPER_FLAGS_4(mve_vrshlsw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
> +
> +DEF_HELPER_FLAGS_4(mve_vrshlub, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
> +DEF_HELPER_FLAGS_4(mve_vrshluh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
> +DEF_HELPER_FLAGS_4(mve_vrshluw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
> +
> DEF_HELPER_FLAGS_4(mve_vqshlsb, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
> DEF_HELPER_FLAGS_4(mve_vqshlsh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
> DEF_HELPER_FLAGS_4(mve_vqshlsw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
> diff --git a/target/arm/mve.decode b/target/arm/mve.decode
> index ebf156b46b5..c30fb2c1536 100644
> --- a/target/arm/mve.decode
> +++ b/target/arm/mve.decode
> @@ -133,6 +133,9 @@ VQSUB_U 111 1 1111 0 . .. ... 0 ... 0 0010 . 1 .
> 1 ... 0 @2op
> VSHL_S 111 0 1111 0 . .. ... 0 ... 0 0100 . 1 . 0 ... 0 @2op_rev
> VSHL_U 111 1 1111 0 . .. ... 0 ... 0 0100 . 1 . 0 ... 0 @2op_rev
>
> +VRSHL_S 111 0 1111 0 . .. ... 0 ... 0 0101 . 1 . 0 ... 0 @2op_rev
> +VRSHL_U 111 1 1111 0 . .. ... 0 ... 0 0101 . 1 . 0 ... 0 @2op_rev
> +
> VQSHL_S 111 0 1111 0 . .. ... 0 ... 0 0100 . 1 . 1 ... 0 @2op_rev
> VQSHL_U 111 1 1111 0 . .. ... 0 ... 0 0100 . 1 . 1 ... 0 @2op_rev
>
> diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
> index 5da1899f3d8..cd6b963849c 100644
> --- a/target/arm/mve_helper.c
> +++ b/target/arm/mve_helper.c
> @@ -538,9 +538,13 @@ DO_2OP_U(vhsubu, do_vhsub_u)
>
> #define DO_VSHLS(N, M) do_sqrshl_bhs(N, (int8_t)(M), sizeof(N) * 8, false,
> NULL)
> #define DO_VSHLU(N, M) do_uqrshl_bhs(N, (int8_t)(M), sizeof(N) * 8, false,
> NULL)
> +#define DO_VRSHLS(N, M) do_sqrshl_bhs(N, (int8_t)(M), sizeof(N) * 8, true,
> NULL)
> +#define DO_VRSHLU(N, M) do_uqrshl_bhs(N, (int8_t)(M), sizeof(N) * 8, true,
> NULL)
>
> DO_2OP_S(vshls, DO_VSHLS)
> DO_2OP_U(vshlu, DO_VSHLU)
> +DO_2OP_S(vrshls, DO_VRSHLS)
> +DO_2OP_U(vrshlu, DO_VRSHLU)
>
> static inline int32_t do_sat_bhw(int64_t val, int64_t min, int64_t max, bool
> *s)
> {
> diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
> index 487ac3185c6..d75cc377fee 100644
> --- a/target/arm/translate-mve.c
> +++ b/target/arm/translate-mve.c
> @@ -404,6 +404,8 @@ DO_2OP(VQSUB_S, vqsubs)
> DO_2OP(VQSUB_U, vqsubu)
> DO_2OP(VSHL_S, vshls)
> DO_2OP(VSHL_U, vshlu)
> +DO_2OP(VRSHL_S, vrshls)
> +DO_2OP(VRSHL_U, vrshlu)
> DO_2OP(VQSHL_S, vqshls)
> DO_2OP(VQSHL_U, vqshlu)
> DO_2OP(VQRSHL_S, vqrshls)
>
- [PATCH v3 23/44] target/arm: Implement MVE VSUB, VMUL (scalar), (continued)
- [PATCH v3 23/44] target/arm: Implement MVE VSUB, VMUL (scalar), Peter Maydell, 2021/06/17
- [PATCH v3 28/44] target/arm: Implement MVE VQDMULH and VQRDMULH (scalar), Peter Maydell, 2021/06/17
- [PATCH v3 22/44] target/arm: Implement MVE VADD (scalar), Peter Maydell, 2021/06/17
- [PATCH v3 25/44] target/arm: Implement MVE VBRSR, Peter Maydell, 2021/06/17
- [PATCH v3 26/44] target/arm: Implement MVE VPST, Peter Maydell, 2021/06/17
- [PATCH v3 27/44] target/arm: Implement MVE VQADD and VQSUB, Peter Maydell, 2021/06/17
- [PATCH v3 21/44] target/arm: Implement MVE VRMLALDAVH, VRMLSLDAVH, Peter Maydell, 2021/06/17
- [PATCH v3 24/44] target/arm: Implement MVE VHADD, VHSUB (scalar), Peter Maydell, 2021/06/17
- [PATCH v3 30/44] target/arm: Implement MVE VQDMULH, VQRDMULH (vector), Peter Maydell, 2021/06/17
- [PATCH v3 35/44] target/arm: Implmement MVE VRSHL, Peter Maydell, 2021/06/17
- Re: [PATCH v3 35/44] target/arm: Implmement MVE VRSHL,
Claudio Fontana <=
- [PATCH v3 32/44] target/arm: Implement MVE VQSHL (vector), Peter Maydell, 2021/06/17
- [PATCH v3 29/44] target/arm: Implement MVE VQDMULL scalar, Peter Maydell, 2021/06/17
- [PATCH v3 31/44] target/arm: Implement MVE VQADD, VQSUB (vector), Peter Maydell, 2021/06/17
- [PATCH v3 34/44] target/arm: Implement MVE VSHL insn, Peter Maydell, 2021/06/17
- [PATCH v3 36/44] target/arm: Implement MVE VQDMLADH and VQRDMLADH, Peter Maydell, 2021/06/17
- [PATCH v3 37/44] target/arm: Implement MVE VQDMLSDH and VQRDMLSDH, Peter Maydell, 2021/06/17
- [PATCH v3 40/44] target/arm: Implement MVE VADC, VSBC, Peter Maydell, 2021/06/17
- [PATCH v3 42/44] target/arm: Implement MVE VHCADD, Peter Maydell, 2021/06/17
- [PATCH v3 41/44] target/arm: Implement MVE VCADD, Peter Maydell, 2021/06/17