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[PATCH v2 46/57] target/arm: Implement MVE VQRSHL
From: |
Peter Maydell |
Subject: |
[PATCH v2 46/57] target/arm: Implement MVE VQRSHL |
Date: |
Mon, 14 Jun 2021 16:09:56 +0100 |
Implement the MV VQRSHL (vector) insn. Again, the code to perform
the actual shifts is borrowed from neon_helper.c.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/helper-mve.h | 8 ++++++++
target/arm/mve.decode | 3 +++
target/arm/mve_helper.c | 6 ++++++
target/arm/translate-mve.c | 2 ++
4 files changed, 19 insertions(+)
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
index 1c5626bb726..42be99ad526 100644
--- a/target/arm/helper-mve.h
+++ b/target/arm/helper-mve.h
@@ -177,6 +177,14 @@ DEF_HELPER_FLAGS_4(mve_vqshlub, TCG_CALL_NO_WG, void, env,
ptr, ptr, ptr)
DEF_HELPER_FLAGS_4(mve_vqshluh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
DEF_HELPER_FLAGS_4(mve_vqshluw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+DEF_HELPER_FLAGS_4(mve_vqrshlsb, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+DEF_HELPER_FLAGS_4(mve_vqrshlsh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+DEF_HELPER_FLAGS_4(mve_vqrshlsw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+
+DEF_HELPER_FLAGS_4(mve_vqrshlub, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+DEF_HELPER_FLAGS_4(mve_vqrshluh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+DEF_HELPER_FLAGS_4(mve_vqrshluw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+
DEF_HELPER_FLAGS_4(mve_vadd_scalarb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(mve_vadd_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(mve_vadd_scalarw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
index 2c37e265765..e78eab6d659 100644
--- a/target/arm/mve.decode
+++ b/target/arm/mve.decode
@@ -133,6 +133,9 @@ VQSUB_U 111 1 1111 0 . .. ... 0 ... 0 0010 . 1 . 1
... 0 @2op
VQSHL_S 111 0 1111 0 . .. ... 0 ... 0 0100 . 1 . 1 ... 0 @2op_rev
VQSHL_U 111 1 1111 0 . .. ... 0 ... 0 0100 . 1 . 1 ... 0 @2op_rev
+VQRSHL_S 111 0 1111 0 . .. ... 0 ... 0 0101 . 1 . 1 ... 0 @2op_rev
+VQRSHL_U 111 1 1111 0 . .. ... 0 ... 0 0101 . 1 . 1 ... 0 @2op_rev
+
# Vector miscellaneous
VCLS 1111 1111 1 . 11 .. 00 ... 0 0100 01 . 0 ... 0 @1op
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
index 31ee057db2e..3464dd311f1 100644
--- a/target/arm/mve_helper.c
+++ b/target/arm/mve_helper.c
@@ -622,9 +622,15 @@ DO_2OP_SAT(vqsubsw, 4, int32_t, DO_SQSUB_W)
WRAP_QRSHL_HELPER(do_sqrshl_bhs, N, M, false, satp)
#define DO_UQSHL_OP(N, M, satp) \
WRAP_QRSHL_HELPER(do_uqrshl_bhs, N, M, false, satp)
+#define DO_SQRSHL_OP(N, M, satp) \
+ WRAP_QRSHL_HELPER(do_sqrshl_bhs, N, M, true, satp)
+#define DO_UQRSHL_OP(N, M, satp) \
+ WRAP_QRSHL_HELPER(do_uqrshl_bhs, N, M, true, satp)
DO_2OP_SAT_S(vqshls, DO_SQSHL_OP)
DO_2OP_SAT_U(vqshlu, DO_UQSHL_OP)
+DO_2OP_SAT_S(vqrshls, DO_SQRSHL_OP)
+DO_2OP_SAT_U(vqrshlu, DO_UQRSHL_OP)
#define DO_2OP_SCALAR(OP, ESIZE, TYPE, FN) \
void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
index bde62bf2445..ac0114c8358 100644
--- a/target/arm/translate-mve.c
+++ b/target/arm/translate-mve.c
@@ -404,6 +404,8 @@ DO_2OP(VQSUB_S, vqsubs)
DO_2OP(VQSUB_U, vqsubu)
DO_2OP(VQSHL_S, vqshls)
DO_2OP(VQSHL_U, vqshlu)
+DO_2OP(VQRSHL_S, vqrshls)
+DO_2OP(VQRSHL_U, vqrshlu)
static bool do_2op_scalar(DisasContext *s, arg_2scalar *a,
MVEGenTwoOpScalarFn fn)
--
2.20.1
- [PATCH v2 42/57] target/arm: Implement MVE VQDMULL scalar, (continued)
- [PATCH v2 42/57] target/arm: Implement MVE VQDMULL scalar, Peter Maydell, 2021/06/14
- [PATCH v2 40/57] target/arm: Implement MVE VQADD and VQSUB, Peter Maydell, 2021/06/14
- [PATCH v2 36/57] target/arm: Implement MVE VSUB, VMUL (scalar), Peter Maydell, 2021/06/14
- [PATCH v2 39/57] target/arm: Implement MVE VPST, Peter Maydell, 2021/06/14
- [PATCH v2 41/57] target/arm: Implement MVE VQDMULH and VQRDMULH (scalar), Peter Maydell, 2021/06/14
- [PATCH v2 44/57] target/arm: Implement MVE VQADD, VQSUB (vector), Peter Maydell, 2021/06/14
- [PATCH v2 45/57] target/arm: Implement MVE VQSHL (vector), Peter Maydell, 2021/06/14
- [PATCH v2 47/57] target/arm: Implement MVE VSHL insn, Peter Maydell, 2021/06/14
- [PATCH v2 50/57] target/arm: Implement MVE VQDMLSDH and VQRDMLSDH, Peter Maydell, 2021/06/14
- [PATCH v2 46/57] target/arm: Implement MVE VQRSHL,
Peter Maydell <=
- [PATCH v2 48/57] target/arm: Implmement MVE VRSHL, Peter Maydell, 2021/06/14
- [PATCH v2 43/57] target/arm: Implement MVE VQDMULH, VQRDMULH (vector), Peter Maydell, 2021/06/14
- [PATCH v2 51/57] target/arm: Implement MVE VQDMULL (vector), Peter Maydell, 2021/06/14
- [PATCH v2 52/57] target/arm: Implement MVE VRHADD, Peter Maydell, 2021/06/14
- [PATCH v2 55/57] target/arm: Implement MVE VHCADD, Peter Maydell, 2021/06/14
- [PATCH v2 49/57] target/arm: Implement MVE VQDMLADH and VQRDMLADH, Peter Maydell, 2021/06/14
- [PATCH v2 56/57] target/arm: Implement MVE VADDV, Peter Maydell, 2021/06/14
- [PATCH v2 57/57] target/arm: Make VMOV scalar <-> gpreg beatwise for MVE, Peter Maydell, 2021/06/14
- [PATCH v2 53/57] target/arm: Implement MVE VADC, VSBC, Peter Maydell, 2021/06/14