[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [PATCH 20/55] target/arm: Implement MVE VDUP
From: |
Peter Maydell |
Subject: |
Re: [PATCH 20/55] target/arm: Implement MVE VDUP |
Date: |
Wed, 9 Jun 2021 11:06:43 +0100 |
On Wed, 9 Jun 2021 at 00:17, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 6/7/21 9:57 AM, Peter Maydell wrote:
> > +#define DO_VDUP(OP, ESIZE, TYPE, H) \
> > + void HELPER(mve_##OP)(CPUARMState *env, void *vd, uint32_t val) \
> > + { \
> > + TYPE *d = vd; \
> > + uint16_t mask = mve_element_mask(env); \
> > + unsigned e; \
> > + for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \
> > + uint64_t bytemask = mask_to_bytemask##ESIZE(mask); \
> > + d[H(e)] &= ~bytemask; \
> > + d[H(e)] |= (val & bytemask); \
> > + } \
> > + mve_advance_vpt(env); \
> > + }
> > +
> > +DO_VDUP(vdupb, 1, uint8_t, H1)
> > +DO_VDUP(vduph, 2, uint16_t, H2)
> > +DO_VDUP(vdupw, 4, uint32_t, H4)
>
> Hmm. I think the masking should be done at either uint32_t or uint64_t.
> Doing
> it byte-by-byte is wasteful.
Mmm. I think some of this structure is holdover from an initial
misinterpretation
of the spec that all these ops looked at the predicate bit for the LS byte
of the element to see if the entire element was acted upon, in which case
you do need to work element-by-element with the right size. (This is actually
true for some operations, but mostly the predicate bits do bytewise masking
and can give you a partial chunk of a result element, as here.)
-- PMM
- [PATCH 34/55] target/arm: Implement MVE VSUB, VMUL (scalar), (continued)
- [PATCH 34/55] target/arm: Implement MVE VSUB, VMUL (scalar), Peter Maydell, 2021/06/07
- [PATCH 39/55] target/arm: Implement MVE VQDMULH and VQRDMULH (scalar), Peter Maydell, 2021/06/07
- [PATCH 35/55] target/arm: Implement MVE VHADD, VHSUB (scalar), Peter Maydell, 2021/06/07
- [PATCH 19/55] target/arm: Implement MVE VNEG, Peter Maydell, 2021/06/07
- [PATCH 20/55] target/arm: Implement MVE VDUP, Peter Maydell, 2021/06/07
- [PATCH 40/55] target/arm: Implement MVE VQDMULL scalar, Peter Maydell, 2021/06/07
- [PATCH 41/55] target/arm: Implement MVE VQDMULH, VQRDMULH (vector), Peter Maydell, 2021/06/07
- [PATCH 38/55] target/arm: Implement MVE VQADD and VQSUB, Peter Maydell, 2021/06/07
- [PATCH 44/55] target/arm: Implement MVE VQRSHL, Peter Maydell, 2021/06/07
- [PATCH 32/55] target/arm: Implement MVE VRMLALDAVH, VRMLSLDAVH, Peter Maydell, 2021/06/07