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[PATCH 46/55] target/arm: Implement MVE VRSHL
From: |
Peter Maydell |
Subject: |
[PATCH 46/55] target/arm: Implement MVE VRSHL |
Date: |
Mon, 7 Jun 2021 17:58:12 +0100 |
Implement the MVE VRSHL insn (vector form).
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/helper-mve.h | 8 ++++++++
target/arm/mve.decode | 3 +++
target/arm/mve_helper.c | 36 ++++++++++++++++++++++++++++++++++++
target/arm/translate-mve.c | 2 ++
4 files changed, 49 insertions(+)
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
index 6ef01d367b4..6939cf84c57 100644
--- a/target/arm/helper-mve.h
+++ b/target/arm/helper-mve.h
@@ -179,6 +179,14 @@ DEF_HELPER_FLAGS_4(mve_vshlub, TCG_CALL_NO_WG, void, env,
ptr, ptr, ptr)
DEF_HELPER_FLAGS_4(mve_vshluh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
DEF_HELPER_FLAGS_4(mve_vshluw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+DEF_HELPER_FLAGS_4(mve_vrshlsb, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+DEF_HELPER_FLAGS_4(mve_vrshlsh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+DEF_HELPER_FLAGS_4(mve_vrshlsw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+
+DEF_HELPER_FLAGS_4(mve_vrshlub, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+DEF_HELPER_FLAGS_4(mve_vrshluh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+DEF_HELPER_FLAGS_4(mve_vrshluw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+
DEF_HELPER_FLAGS_4(mve_vqshlsb, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
DEF_HELPER_FLAGS_4(mve_vqshlsh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
DEF_HELPER_FLAGS_4(mve_vqshlsw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
index ebf156b46b5..c30fb2c1536 100644
--- a/target/arm/mve.decode
+++ b/target/arm/mve.decode
@@ -133,6 +133,9 @@ VQSUB_U 111 1 1111 0 . .. ... 0 ... 0 0010 . 1 . 1
... 0 @2op
VSHL_S 111 0 1111 0 . .. ... 0 ... 0 0100 . 1 . 0 ... 0 @2op_rev
VSHL_U 111 1 1111 0 . .. ... 0 ... 0 0100 . 1 . 0 ... 0 @2op_rev
+VRSHL_S 111 0 1111 0 . .. ... 0 ... 0 0101 . 1 . 0 ... 0 @2op_rev
+VRSHL_U 111 1 1111 0 . .. ... 0 ... 0 0101 . 1 . 0 ... 0 @2op_rev
+
VQSHL_S 111 0 1111 0 . .. ... 0 ... 0 0100 . 1 . 1 ... 0 @2op_rev
VQSHL_U 111 1 1111 0 . .. ... 0 ... 0 0100 . 1 . 1 ... 0 @2op_rev
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
index c95d5a0fd8e..9c23e6b9b28 100644
--- a/target/arm/mve_helper.c
+++ b/target/arm/mve_helper.c
@@ -538,6 +538,42 @@ static inline int32_t do_sshl(int32_t n, int8_t shift, int
esize)
DO_2OP_S(vshls, DO_VSHLS)
DO_2OP_U(vshlu, DO_VSHLU)
+static inline uint32_t do_urshl(uint32_t n, int8_t shift, int esize)
+{
+ if (shift >= esize || shift < -esize) {
+ return 0;
+ } else if (shift == -esize) {
+ return n >> (-esize - 1);
+ } else if (shift < 0) {
+ /* Use 64 bit intermediate: adding the rounding const might overflow */
+ uint64_t r = (uint64_t)n + (1 << (-1 - shift));
+ return r >> -shift;
+ } else {
+ return n << shift;
+ }
+}
+
+static inline int32_t do_srshl(int32_t n, int8_t shift, int esize)
+{
+ if (shift >= esize || shift <= -esize) {
+ return 0;
+ } else if (shift == -esize) {
+ return n >> (-esize - 1);
+ } else if (shift < 0) {
+ /* Use 64 bit intermediate: adding the rounding const might overflow */
+ int64_t r = (int64_t)n + (1 << (-1 - shift));
+ return r >> -shift;
+ } else {
+ return n << shift;
+ }
+}
+
+#define DO_VRSHLS(N, M) do_srshl(N, M, sizeof(N) * 8)
+#define DO_VRSHLU(N, M) do_urshl(N, M, sizeof(N) * 8)
+
+DO_2OP_S(vrshls, DO_VRSHLS)
+DO_2OP_U(vrshlu, DO_VRSHLU)
+
static inline int32_t do_sat_bhw(int64_t val, int64_t min, int64_t max, bool
*s)
{
if (val > max) {
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
index 6eaa99bc0f5..6bc32379172 100644
--- a/target/arm/translate-mve.c
+++ b/target/arm/translate-mve.c
@@ -423,6 +423,8 @@ DO_2OP(VQSUB_S, vqsubs)
DO_2OP(VQSUB_U, vqsubu)
DO_2OP(VSHL_S, vshls)
DO_2OP(VSHL_U, vshlu)
+DO_2OP(VRSHL_S, vrshls)
+DO_2OP(VRSHL_U, vrshlu)
DO_2OP(VQSHL_S, vqshls)
DO_2OP(VQSHL_U, vqshlu)
DO_2OP(VQRSHL_S, vqrshls)
--
2.20.1
- Re: [PATCH 38/55] target/arm: Implement MVE VQADD and VQSUB, (continued)
- [PATCH 44/55] target/arm: Implement MVE VQRSHL, Peter Maydell, 2021/06/07
- [PATCH 32/55] target/arm: Implement MVE VRMLALDAVH, VRMLSLDAVH, Peter Maydell, 2021/06/07
- [PATCH 45/55] target/arm: Implement MVE VSHL insn, Peter Maydell, 2021/06/07
- [PATCH 42/55] target/arm: Implement MVE VQADD, VQSUB (vector), Peter Maydell, 2021/06/07
- [PATCH 46/55] target/arm: Implement MVE VRSHL,
Peter Maydell <=
- [PATCH 33/55] target/arm: Implement MVE VADD (scalar), Peter Maydell, 2021/06/07
- [PATCH 50/55] target/arm: Implement MVE VRHADD, Peter Maydell, 2021/06/07
- [PATCH 49/55] target/arm: Implement MVE VQDMULL (vector), Peter Maydell, 2021/06/07
- [PATCH 51/55] target/arm: Implement MVE VADC, VSBC, Peter Maydell, 2021/06/07