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[PATCH 36/55] target/arm: Implement MVE VBRSR
From: |
Peter Maydell |
Subject: |
[PATCH 36/55] target/arm: Implement MVE VBRSR |
Date: |
Mon, 7 Jun 2021 17:58:02 +0100 |
Implement the MVE VBRSR insn, which reverses a specified
number of bits in each element, setting the rest to zero.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/helper-mve.h | 4 ++++
target/arm/mve.decode | 1 +
target/arm/mve_helper.c | 43 ++++++++++++++++++++++++++++++++++++++
target/arm/translate-mve.c | 1 +
4 files changed, 49 insertions(+)
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
index 5853bd34687..1f77a661b9b 100644
--- a/target/arm/helper-mve.h
+++ b/target/arm/helper-mve.h
@@ -175,6 +175,10 @@ DEF_HELPER_FLAGS_4(mve_vhsubu_scalarb, TCG_CALL_NO_WG,
void, env, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(mve_vhsubu_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr,
i32)
DEF_HELPER_FLAGS_4(mve_vhsubu_scalarw, TCG_CALL_NO_WG, void, env, ptr, ptr,
i32)
+DEF_HELPER_FLAGS_4(mve_vbrsrb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vbrsrh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vbrsrw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+
DEF_HELPER_FLAGS_4(mve_vmlaldavsh, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64)
DEF_HELPER_FLAGS_4(mve_vmlaldavsw, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64)
DEF_HELPER_FLAGS_4(mve_vmlaldavxsh, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64)
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
index 5c332b04a7c..a3dbdb72a5c 100644
--- a/target/arm/mve.decode
+++ b/target/arm/mve.decode
@@ -167,3 +167,4 @@ VHADD_S_scalar 1110 1110 0 . .. ... 0 ... 0 1111 . 100
.... @2scalar
VHADD_U_scalar 1111 1110 0 . .. ... 0 ... 0 1111 . 100 .... @2scalar
VHSUB_S_scalar 1110 1110 0 . .. ... 0 ... 1 1111 . 100 .... @2scalar
VHSUB_U_scalar 1111 1110 0 . .. ... 0 ... 1 1111 . 100 .... @2scalar
+VBRSR 1111 1110 0 . .. ... 1 ... 1 1110 . 110 .... @2scalar
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
index dbcf4c24949..25426fae992 100644
--- a/target/arm/mve_helper.c
+++ b/target/arm/mve_helper.c
@@ -513,6 +513,49 @@ DO_2OP_SCALAR_U(vhaddu_scalar, do_vhadd_u)
DO_2OP_SCALAR_S(vhsubs_scalar, do_vhsub_s)
DO_2OP_SCALAR_U(vhsubu_scalar, do_vhsub_u)
+static inline uint32_t do_vbrsrb(uint32_t n, uint32_t m)
+{
+ m &= 0xff;
+ if (m == 0) {
+ return 0;
+ }
+ n = revbit8(n);
+ if (m < 8) {
+ n >>= 8 - m;
+ }
+ return n;
+}
+
+static inline uint32_t do_vbrsrh(uint32_t n, uint32_t m)
+{
+ m &= 0xff;
+ if (m == 0) {
+ return 0;
+ }
+ n = revbit16(n);
+ if (m < 16) {
+ n >>= 16 - m;
+ }
+ return n;
+}
+
+static inline uint32_t do_vbrsrw(uint32_t n, uint32_t m)
+{
+ m &= 0xff;
+ if (m == 0) {
+ return 0;
+ }
+ n = revbit32(n);
+ if (m < 32) {
+ n >>= 32 - m;
+ }
+ return n;
+}
+
+DO_2OP_SCALAR(vbrsrb, 1, uint8_t, H1, do_vbrsrb)
+DO_2OP_SCALAR(vbrsrh, 2, uint16_t, H2, do_vbrsrh)
+DO_2OP_SCALAR(vbrsrw, 4, uint32_t, H4, do_vbrsrw)
+
/*
* Multiply add long dual accumulate ops.
*/
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
index 8dfc52d8027..b7bf7d0960f 100644
--- a/target/arm/translate-mve.c
+++ b/target/arm/translate-mve.c
@@ -469,6 +469,7 @@ DO_2OP_SCALAR(VHADD_S_scalar, vhadds_scalar)
DO_2OP_SCALAR(VHADD_U_scalar, vhaddu_scalar)
DO_2OP_SCALAR(VHSUB_S_scalar, vhsubs_scalar)
DO_2OP_SCALAR(VHSUB_U_scalar, vhsubu_scalar)
+DO_2OP_SCALAR(VBRSR, vbrsr)
static bool do_long_dual_acc(DisasContext *s, arg_vmlaldav *a,
MVEGenDualAccOpFn *fn)
--
2.20.1
- Re: [PATCH 13/55] target/arm: Implement MVE VCLZ, (continued)
[PATCH 17/55] target/arm: Implement MVE VMVN (register), Peter Maydell, 2021/06/07
[PATCH 26/55] target/arm: Implement MVE VABD, Peter Maydell, 2021/06/07
[PATCH 21/55] target/arm: Implement MVE VAND, VBIC, VORR, VORN, VEOR, Peter Maydell, 2021/06/07
[PATCH 30/55] target/arm: Implement MVE VMLSLDAV, Peter Maydell, 2021/06/07
[PATCH 36/55] target/arm: Implement MVE VBRSR,
Peter Maydell <=
[PATCH 27/55] target/arm: Implement MVE VHADD, VHSUB, Peter Maydell, 2021/06/07
[PATCH 37/55] target/arm: Implement MVE VPST, Peter Maydell, 2021/06/07
[PATCH 18/55] target/arm: Implement MVE VABS, Peter Maydell, 2021/06/07
[PATCH 25/55] target/arm: Implement MVE VMAX, VMIN, Peter Maydell, 2021/06/07
[PATCH 28/55] target/arm: Implement MVE VMULL, Peter Maydell, 2021/06/07