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[PATCH v6 67/82] target/arm: Implement SVE2 FCVTXNT, FCVTX
From: |
Richard Henderson |
Subject: |
[PATCH v6 67/82] target/arm: Implement SVE2 FCVTXNT, FCVTX |
Date: |
Fri, 30 Apr 2021 13:25:55 -0700 |
From: Stephen Long <steplong@quicinc.com>
Signed-off-by: Stephen Long <steplong@quicinc.com>
Message-Id: <20200428174332.17162-4-steplong@quicinc.com>
[rth: Use do_frint_mode, which avoids a specific runtime helper.]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/sve.decode | 2 ++
target/arm/translate-sve.c | 49 ++++++++++++++++++++++++++++++--------
2 files changed, 41 insertions(+), 10 deletions(-)
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
index fb998f5f34..46153d6a84 100644
--- a/target/arm/sve.decode
+++ b/target/arm/sve.decode
@@ -1533,6 +1533,8 @@ SM4EKEY 01000101 00 1 ..... 11110 0 ..... .....
@rd_rn_rm_e0
RAX1 01000101 00 1 ..... 11110 1 ..... ..... @rd_rn_rm_e0
### SVE2 floating-point convert precision odd elements
+FCVTXNT_ds 01100100 00 0010 10 101 ... ..... ..... @rd_pg_rn_e0
+FCVTX_ds 01100101 00 0010 10 101 ... ..... ..... @rd_pg_rn_e0
FCVTNT_sh 01100100 10 0010 00 101 ... ..... ..... @rd_pg_rn_e0
FCVTLT_hs 01100100 10 0010 01 101 ... ..... ..... @rd_pg_rn_e0
FCVTNT_ds 01100100 11 0010 10 101 ... ..... ..... @rd_pg_rn_e0
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index f5bf122204..87e5c8ac63 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -4715,11 +4715,9 @@ static bool trans_FRINTX(DisasContext *s, arg_rpr_esz *a)
return do_zpz_ptr(s, a->rd, a->rn, a->pg, a->esz == MO_16, fns[a->esz -
1]);
}
-static bool do_frint_mode(DisasContext *s, arg_rpr_esz *a, int mode)
+static bool do_frint_mode(DisasContext *s, arg_rpr_esz *a,
+ int mode, gen_helper_gvec_3_ptr *fn)
{
- if (a->esz == 0) {
- return false;
- }
if (sve_access_check(s)) {
unsigned vsz = vec_full_reg_size(s);
TCGv_i32 tmode = tcg_const_i32(mode);
@@ -4730,7 +4728,7 @@ static bool do_frint_mode(DisasContext *s, arg_rpr_esz
*a, int mode)
tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, a->rd),
vec_full_reg_offset(s, a->rn),
pred_full_reg_offset(s, a->pg),
- status, vsz, vsz, 0, frint_fns[a->esz - 1]);
+ status, vsz, vsz, 0, fn);
gen_helper_set_rmode(tmode, tmode, status);
tcg_temp_free_i32(tmode);
@@ -4741,27 +4739,42 @@ static bool do_frint_mode(DisasContext *s, arg_rpr_esz
*a, int mode)
static bool trans_FRINTN(DisasContext *s, arg_rpr_esz *a)
{
- return do_frint_mode(s, a, float_round_nearest_even);
+ if (a->esz == 0) {
+ return false;
+ }
+ return do_frint_mode(s, a, float_round_nearest_even, frint_fns[a->esz -
1]);
}
static bool trans_FRINTP(DisasContext *s, arg_rpr_esz *a)
{
- return do_frint_mode(s, a, float_round_up);
+ if (a->esz == 0) {
+ return false;
+ }
+ return do_frint_mode(s, a, float_round_up, frint_fns[a->esz - 1]);
}
static bool trans_FRINTM(DisasContext *s, arg_rpr_esz *a)
{
- return do_frint_mode(s, a, float_round_down);
+ if (a->esz == 0) {
+ return false;
+ }
+ return do_frint_mode(s, a, float_round_down, frint_fns[a->esz - 1]);
}
static bool trans_FRINTZ(DisasContext *s, arg_rpr_esz *a)
{
- return do_frint_mode(s, a, float_round_to_zero);
+ if (a->esz == 0) {
+ return false;
+ }
+ return do_frint_mode(s, a, float_round_to_zero, frint_fns[a->esz - 1]);
}
static bool trans_FRINTA(DisasContext *s, arg_rpr_esz *a)
{
- return do_frint_mode(s, a, float_round_ties_away);
+ if (a->esz == 0) {
+ return false;
+ }
+ return do_frint_mode(s, a, float_round_ties_away, frint_fns[a->esz - 1]);
}
static bool trans_FRECPX(DisasContext *s, arg_rpr_esz *a)
@@ -8202,3 +8215,19 @@ static bool trans_FCVTLT_sd(DisasContext *s, arg_rpr_esz
*a)
}
return do_zpz_ptr(s, a->rd, a->rn, a->pg, false,
gen_helper_sve2_fcvtlt_sd);
}
+
+static bool trans_FCVTX_ds(DisasContext *s, arg_rpr_esz *a)
+{
+ if (!dc_isar_feature(aa64_sve2, s)) {
+ return false;
+ }
+ return do_frint_mode(s, a, float_round_to_odd, gen_helper_sve_fcvt_ds);
+}
+
+static bool trans_FCVTXNT_ds(DisasContext *s, arg_rpr_esz *a)
+{
+ if (!dc_isar_feature(aa64_sve2, s)) {
+ return false;
+ }
+ return do_frint_mode(s, a, float_round_to_odd, gen_helper_sve2_fcvtnt_ds);
+}
--
2.25.1
- [PATCH v6 72/82] target/arm: Implement SVE2 bitwise shift immediate, (continued)
- [PATCH v6 72/82] target/arm: Implement SVE2 bitwise shift immediate, Richard Henderson, 2021/04/30
- [PATCH v6 44/82] target/arm: Implement SVE2 scatter store insns, Richard Henderson, 2021/04/30
- [PATCH v6 61/82] target/arm: Implement SVE2 crypto unary operations, Richard Henderson, 2021/04/30
- [PATCH v6 76/82] target/arm: Remove unused fpst from VDOT_scalar, Richard Henderson, 2021/04/30
- [PATCH v6 64/82] target/arm: Implement SVE2 TBL, TBX, Richard Henderson, 2021/04/30
- [PATCH v6 63/82] target/arm: Implement SVE2 crypto constructive binary operations, Richard Henderson, 2021/04/30
- [PATCH v6 74/82] target/arm: Implement aarch64 SUDOT, USDOT, Richard Henderson, 2021/04/30
- [PATCH v6 65/82] target/arm: Implement SVE2 FCVTNT, Richard Henderson, 2021/04/30
- [PATCH v6 71/82] target/arm: Implement 128-bit ZIP, UZP, TRN, Richard Henderson, 2021/04/30
- [PATCH v6 49/82] target/arm: Pass separate addend to FCMLA helpers, Richard Henderson, 2021/04/30
- [PATCH v6 67/82] target/arm: Implement SVE2 FCVTXNT, FCVTX,
Richard Henderson <=
- [PATCH v6 73/82] target/arm: Implement SVE2 fp multiply-add long, Richard Henderson, 2021/04/30
- [PATCH v6 56/82] target/arm: Implement SVE2 saturating multiply (indexed), Richard Henderson, 2021/04/30
- [PATCH v6 62/82] target/arm: Implement SVE2 crypto destructive binary operations, Richard Henderson, 2021/04/30
- [PATCH v6 69/82] target/arm: Share table of sve load functions, Richard Henderson, 2021/04/30
- [PATCH v6 78/82] target/arm: Split decode of VSDOT and VUDOT, Richard Henderson, 2021/04/30
- [PATCH v6 66/82] target/arm: Implement SVE2 FCVTLT, Richard Henderson, 2021/04/30
- [PATCH v6 70/82] target/arm: Implement SVE2 LD1RO, Richard Henderson, 2021/04/30
- [PATCH v6 79/82] target/arm: Implement aarch32 VSUDOT, VUSDOT, Richard Henderson, 2021/04/30
- [PATCH v6 75/82] target/arm: Split out do_neon_ddda_fpst, Richard Henderson, 2021/04/30
- [PATCH v6 77/82] target/arm: Fix decode for VDOT (indexed), Richard Henderson, 2021/04/30