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[PATCH v6 40/82] target/arm: Implement SVE2 SUBHNB, SUBHNT
From: |
Richard Henderson |
Subject: |
[PATCH v6 40/82] target/arm: Implement SVE2 SUBHNB, SUBHNT |
Date: |
Fri, 30 Apr 2021 13:25:28 -0700 |
From: Stephen Long <steplong@quicinc.com>
Signed-off-by: Stephen Long <steplong@quicinc.com>
Message-Id: <20200417162231.10374-4-steplong@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/helper-sve.h | 8 ++++++++
target/arm/sve.decode | 2 ++
target/arm/sve_helper.c | 10 ++++++++++
target/arm/translate-sve.c | 3 +++
4 files changed, 23 insertions(+)
diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h
index 8d95c87694..3642e7c820 100644
--- a/target/arm/helper-sve.h
+++ b/target/arm/helper-sve.h
@@ -2525,6 +2525,14 @@ DEF_HELPER_FLAGS_4(sve2_raddhnt_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve2_raddhnt_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve2_raddhnt_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(sve2_subhnb_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(sve2_subhnb_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(sve2_subhnb_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(sve2_subhnt_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(sve2_subhnt_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(sve2_subhnt_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+
DEF_HELPER_FLAGS_5(sve2_match_ppzz_b, TCG_CALL_NO_RWG,
i32, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve2_match_ppzz_h, TCG_CALL_NO_RWG,
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
index dfcfab4bc0..c68bfcf6ed 100644
--- a/target/arm/sve.decode
+++ b/target/arm/sve.decode
@@ -1326,6 +1326,8 @@ ADDHNB 01000101 .. 1 ..... 011 000 ..... .....
@rd_rn_rm
ADDHNT 01000101 .. 1 ..... 011 001 ..... ..... @rd_rn_rm
RADDHNB 01000101 .. 1 ..... 011 010 ..... ..... @rd_rn_rm
RADDHNT 01000101 .. 1 ..... 011 011 ..... ..... @rd_rn_rm
+SUBHNB 01000101 .. 1 ..... 011 100 ..... ..... @rd_rn_rm
+SUBHNT 01000101 .. 1 ..... 011 101 ..... ..... @rd_rn_rm
### SVE2 Character Match
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
index e6f6e3d5fa..0df70effe3 100644
--- a/target/arm/sve_helper.c
+++ b/target/arm/sve_helper.c
@@ -2136,6 +2136,7 @@ void HELPER(NAME)(void *vd, void *vn, void *vm, uint32_t
desc) \
#define DO_ADDHN(N, M, SH) ((N + M) >> SH)
#define DO_RADDHN(N, M, SH) ((N + M + ((__typeof(N))1 << (SH - 1))) >> SH)
+#define DO_SUBHN(N, M, SH) ((N - M) >> SH)
DO_BINOPNB(sve2_addhnb_h, uint16_t, uint8_t, 8, DO_ADDHN)
DO_BINOPNB(sve2_addhnb_s, uint32_t, uint16_t, 16, DO_ADDHN)
@@ -2153,6 +2154,15 @@ DO_BINOPNT(sve2_raddhnt_h, uint16_t, uint8_t, 8, H1_2,
H1, DO_RADDHN)
DO_BINOPNT(sve2_raddhnt_s, uint32_t, uint16_t, 16, H1_4, H1_2, DO_RADDHN)
DO_BINOPNT(sve2_raddhnt_d, uint64_t, uint32_t, 32, , H1_4, DO_RADDHN)
+DO_BINOPNB(sve2_subhnb_h, uint16_t, uint8_t, 8, DO_SUBHN)
+DO_BINOPNB(sve2_subhnb_s, uint32_t, uint16_t, 16, DO_SUBHN)
+DO_BINOPNB(sve2_subhnb_d, uint64_t, uint32_t, 32, DO_SUBHN)
+
+DO_BINOPNT(sve2_subhnt_h, uint16_t, uint8_t, 8, H1_2, H1, DO_SUBHN)
+DO_BINOPNT(sve2_subhnt_s, uint32_t, uint16_t, 16, H1_4, H1_2, DO_SUBHN)
+DO_BINOPNT(sve2_subhnt_d, uint64_t, uint32_t, 32, , H1_4, DO_SUBHN)
+
+#undef DO_SUBHN
#undef DO_RADDHN
#undef DO_ADDHN
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index af0d0ab279..55303ba41d 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -7477,6 +7477,9 @@ DO_SVE2_ZZZ_NARROW(ADDHNT, addhnt)
DO_SVE2_ZZZ_NARROW(RADDHNB, raddhnb)
DO_SVE2_ZZZ_NARROW(RADDHNT, raddhnt)
+DO_SVE2_ZZZ_NARROW(SUBHNB, subhnb)
+DO_SVE2_ZZZ_NARROW(SUBHNT, subhnt)
+
static bool do_sve2_ppzz_flags(DisasContext *s, arg_rprr_esz *a,
gen_helper_gvec_flags_4 *fn)
{
--
2.25.1
- [PATCH v6 28/82] target/arm: Implement SVE2 UQSHRN, UQRSHRN, (continued)
- [PATCH v6 28/82] target/arm: Implement SVE2 UQSHRN, UQRSHRN, Richard Henderson, 2021/04/30
- [PATCH v6 31/82] target/arm: Implement SVE2 WHILERW, WHILEWR, Richard Henderson, 2021/04/30
- [PATCH v6 32/82] target/arm: Implement SVE2 bitwise ternary operations, Richard Henderson, 2021/04/30
- [PATCH v6 34/82] target/arm: Implement SVE2 saturating multiply-add long, Richard Henderson, 2021/04/30
- [PATCH v6 33/82] target/arm: Implement SVE2 MATCH, NMATCH, Richard Henderson, 2021/04/30
- [PATCH v6 37/82] target/arm: Implement SVE2 complex integer multiply-add, Richard Henderson, 2021/04/30
- [PATCH v6 38/82] target/arm: Implement SVE2 ADDHNB, ADDHNT, Richard Henderson, 2021/04/30
- [PATCH v6 36/82] target/arm: Implement SVE2 integer multiply-add long, Richard Henderson, 2021/04/30
- [PATCH v6 39/82] target/arm: Implement SVE2 RADDHNB, RADDHNT, Richard Henderson, 2021/04/30
- [PATCH v6 35/82] target/arm: Implement SVE2 saturating multiply-add high, Richard Henderson, 2021/04/30
- [PATCH v6 40/82] target/arm: Implement SVE2 SUBHNB, SUBHNT,
Richard Henderson <=
- [PATCH v6 41/82] target/arm: Implement SVE2 RSUBHNB, RSUBHNT, Richard Henderson, 2021/04/30
- [PATCH v6 46/82] target/arm: Implement SVE2 FMMLA, Richard Henderson, 2021/04/30
- [PATCH v6 43/82] target/arm: Implement SVE2 XAR, Richard Henderson, 2021/04/30
- [PATCH v6 48/82] target/arm: Pass separate addend to {U, S}DOT helpers, Richard Henderson, 2021/04/30
- [PATCH v6 42/82] target/arm: Implement SVE2 HISTCNT, HISTSEG, Richard Henderson, 2021/04/30
- [PATCH v6 47/82] target/arm: Implement SVE2 SPLICE, EXT, Richard Henderson, 2021/04/30
- [PATCH v6 55/82] target/arm: Implement SVE2 saturating multiply-add (indexed), Richard Henderson, 2021/04/30
- [PATCH v6 59/82] target/arm: Implement SVE mixed sign dot product (indexed), Richard Henderson, 2021/04/30
- [PATCH v6 60/82] target/arm: Implement SVE mixed sign dot product, Richard Henderson, 2021/04/30
- [PATCH v6 50/82] target/arm: Split out formats for 2 vectors + 1 index, Richard Henderson, 2021/04/30