Re: [PATCH] target/arm: Flush correct TLBs in tlbi_aa64_vae2is_write()

[Rémi Denis-Courmont]

Le tiistaina 20. huhtikuuta 2021, 15.31.06 EEST Peter Maydell a écrit :
> In tlbi_aa64_vae2is_write() the calculation
>   bits = tlbbits_for_regime(env, secure ? ARMMMUIdx_E2 : ARMMMUIdx_SE2,
>                             pageaddr)
> 
> has the two arms of the ?: expression reversed. Fix the bug.
> 
> Fixes: b6ad6062f1e5
> Reported-by: Rebecca Cran <rebecca@nuviainc.com>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
>  target/arm/helper.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index d9220be7c5a..957f4247010 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -4742,7 +4742,7 @@ static void tlbi_aa64_vae2is_write(CPUARMState *env,
> const ARMCPRegInfo *ri, uint64_t pageaddr = sextract64(value << 12, 0, 56);
>      bool secure = arm_is_secure_below_el3(env);
>      int mask = secure ? ARMMMUIdxBit_SE2 : ARMMMUIdxBit_E2;
> -    int bits = tlbbits_for_regime(env, secure ? ARMMMUIdx_E2 :
> ARMMMUIdx_SE2, +    int bits = tlbbits_for_regime(env, secure ?
> ARMMMUIdx_SE2 : ARMMMUIdx_E2, pageaddr);
> 
>      tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, mask,
> bits);

Reviewed-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>

-- 
Rémi Denis-Courmont
http://www.remlab.net/