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[PATCH v5 78/81] target/arm: Split decode of VSDOT and VUDOT
From: |
Richard Henderson |
Subject: |
[PATCH v5 78/81] target/arm: Split decode of VSDOT and VUDOT |
Date: |
Fri, 16 Apr 2021 14:02:37 -0700 |
Now that we have a common helper, sharing decode does not
save much. Also, this will solve an upcoming naming problem.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/neon-shared.decode | 9 ++++++---
target/arm/translate-neon.c.inc | 30 ++++++++++++++++++++++--------
2 files changed, 28 insertions(+), 11 deletions(-)
diff --git a/target/arm/neon-shared.decode b/target/arm/neon-shared.decode
index facb621450..2d94369750 100644
--- a/target/arm/neon-shared.decode
+++ b/target/arm/neon-shared.decode
@@ -46,8 +46,9 @@ VCMLA 1111 110 rot:2 . 1 . .... .... 1000 . q:1 . 0
.... \
VCADD 1111 110 rot:1 1 . 0 . .... .... 1000 . q:1 . 0 .... \
vm=%vm_dp vn=%vn_dp vd=%vd_dp size=%vcadd_size
-# VUDOT and VSDOT
-VDOT 1111 110 00 . 10 .... .... 1101 . q:1 . u:1 .... \
+VSDOT 1111 110 00 . 10 .... .... 1101 . q:1 . 0 .... \
+ vm=%vm_dp vn=%vn_dp vd=%vd_dp
+VUDOT 1111 110 00 . 10 .... .... 1101 . q:1 . 1 .... \
vm=%vm_dp vn=%vn_dp vd=%vd_dp
# VFM[AS]L
@@ -61,7 +62,9 @@ VCMLA_scalar 1111 1110 0 . rot:2 .... .... 1000 . q:1
index:1 0 vm:4 \
VCMLA_scalar 1111 1110 1 . rot:2 .... .... 1000 . q:1 . 0 .... \
vm=%vm_dp vn=%vn_dp vd=%vd_dp size=2 index=0
-VDOT_scalar 1111 1110 0 . 10 .... .... 1101 . q:1 index:1 u:1 vm:4 \
+VSDOT_scalar 1111 1110 0 . 10 .... .... 1101 . q:1 index:1 0 vm:4 \
+ vn=%vn_dp vd=%vd_dp
+VUDOT_scalar 1111 1110 0 . 10 .... .... 1101 . q:1 index:1 1 vm:4 \
vn=%vn_dp vd=%vd_dp
%vfml_scalar_q0_rm 0:3 5:1
diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc
index d9901c0153..2fd6478d3c 100644
--- a/target/arm/translate-neon.c.inc
+++ b/target/arm/translate-neon.c.inc
@@ -260,15 +260,22 @@ static bool trans_VCADD(DisasContext *s, arg_VCADD *a)
return true;
}
-static bool trans_VDOT(DisasContext *s, arg_VDOT *a)
+static bool trans_VSDOT(DisasContext *s, arg_VSDOT *a)
{
if (!dc_isar_feature(aa32_dp, s)) {
return false;
}
return do_neon_ddda(s, a->q * 7, a->vd, a->vn, a->vm, 0,
- a->u
- ? gen_helper_gvec_udot_b
- : gen_helper_gvec_sdot_b);
+ gen_helper_gvec_sdot_b);
+}
+
+static bool trans_VUDOT(DisasContext *s, arg_VUDOT *a)
+{
+ if (!dc_isar_feature(aa32_dp, s)) {
+ return false;
+ }
+ return do_neon_ddda(s, a->q * 7, a->vd, a->vn, a->vm, 0,
+ gen_helper_gvec_udot_b);
}
static bool trans_VFML(DisasContext *s, arg_VFML *a)
@@ -320,15 +327,22 @@ static bool trans_VCMLA_scalar(DisasContext *s,
arg_VCMLA_scalar *a)
FPST_STD, gen_helper_gvec_fcmlas_idx);
}
-static bool trans_VDOT_scalar(DisasContext *s, arg_VDOT_scalar *a)
+static bool trans_VSDOT_scalar(DisasContext *s, arg_VSDOT_scalar *a)
{
if (!dc_isar_feature(aa32_dp, s)) {
return false;
}
return do_neon_ddda(s, a->q * 6, a->vd, a->vn, a->vm, a->index,
- a->u
- ? gen_helper_gvec_udot_idx_b
- : gen_helper_gvec_sdot_idx_b);
+ gen_helper_gvec_sdot_idx_b);
+}
+
+static bool trans_VUDOT_scalar(DisasContext *s, arg_VUDOT_scalar *a)
+{
+ if (!dc_isar_feature(aa32_dp, s)) {
+ return false;
+ }
+ return do_neon_ddda(s, a->q * 6, a->vd, a->vn, a->vm, a->index,
+ gen_helper_gvec_udot_idx_b);
}
static bool trans_VFML_scalar(DisasContext *s, arg_VFML_scalar *a)
--
2.25.1
- [PATCH v5 59/81] target/arm: Implement SVE mixed sign dot product (indexed), (continued)
- [PATCH v5 59/81] target/arm: Implement SVE mixed sign dot product (indexed), Richard Henderson, 2021/04/16
- [PATCH v5 65/81] target/arm: Implement SVE2 FCVTNT, Richard Henderson, 2021/04/16
- [PATCH v5 67/81] target/arm: Implement SVE2 FCVTXNT, FCVTX, Richard Henderson, 2021/04/16
- [PATCH v5 63/81] target/arm: Implement SVE2 crypto constructive binary operations, Richard Henderson, 2021/04/16
- [PATCH v5 70/81] target/arm: Implement SVE2 LD1RO, Richard Henderson, 2021/04/16
- [PATCH v5 71/81] target/arm: Implement 128-bit ZIP, UZP, TRN, Richard Henderson, 2021/04/16
- [PATCH v5 72/81] target/arm: Implement SVE2 bitwise shift immediate, Richard Henderson, 2021/04/16
- [PATCH v5 73/81] target/arm: Implement SVE2 fp multiply-add long, Richard Henderson, 2021/04/16
- [PATCH v5 75/81] target/arm: Split out do_neon_ddda_fpst, Richard Henderson, 2021/04/16
- [PATCH v5 74/81] target/arm: Implement aarch64 SUDOT, USDOT, Richard Henderson, 2021/04/16
- [PATCH v5 78/81] target/arm: Split decode of VSDOT and VUDOT,
Richard Henderson <=
- [PATCH v5 76/81] target/arm: Remove unused fpst from VDOT_scalar, Richard Henderson, 2021/04/16
- [PATCH v5 77/81] target/arm: Fix decode for VDOT (indexed), Richard Henderson, 2021/04/16
- [PATCH v5 79/81] target/arm: Implement aarch32 VSUDOT, VUSDOT, Richard Henderson, 2021/04/16
- [PATCH v5 80/81] target/arm: Implement integer matrix multiply accumulate, Richard Henderson, 2021/04/16
- [PATCH v5 81/81] target/arm: Enable SVE2 and some extensions, Richard Henderson, 2021/04/16
- Re: [PATCH v5 for-6.1 00/81] target/arm: Implement SVE2, no-reply, 2021/04/16