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[PATCH v5 53/81] target/arm: Implement SVE2 integer multiply-add (indexe
From: |
Richard Henderson |
Subject: |
[PATCH v5 53/81] target/arm: Implement SVE2 integer multiply-add (indexed) |
Date: |
Fri, 16 Apr 2021 14:02:12 -0700 |
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/sve.decode | 8 ++++++++
target/arm/translate-sve.c | 23 +++++++++++++++++++++++
2 files changed, 31 insertions(+)
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
index 65cb0a2206..9bfaf737b7 100644
--- a/target/arm/sve.decode
+++ b/target/arm/sve.decode
@@ -783,6 +783,14 @@ SDOT_zzxw_d 01000100 11 1 ..... 000000 ..... .....
@rrxr_1 esz=3
UDOT_zzxw_s 01000100 10 1 ..... 000001 ..... ..... @rrxr_2 esz=2
UDOT_zzxw_d 01000100 11 1 ..... 000001 ..... ..... @rrxr_1 esz=3
+# SVE2 integer multiply-add (indexed)
+MLA_zzxz_h 01000100 0. 1 ..... 000010 ..... ..... @rrxr_3 esz=1
+MLA_zzxz_s 01000100 10 1 ..... 000010 ..... ..... @rrxr_2 esz=2
+MLA_zzxz_d 01000100 11 1 ..... 000010 ..... ..... @rrxr_1 esz=3
+MLS_zzxz_h 01000100 0. 1 ..... 000011 ..... ..... @rrxr_3 esz=1
+MLS_zzxz_s 01000100 10 1 ..... 000011 ..... ..... @rrxr_2 esz=2
+MLS_zzxz_d 01000100 11 1 ..... 000011 ..... ..... @rrxr_1 esz=3
+
# SVE2 integer multiply (indexed)
MUL_zzx_h 01000100 0. 1 ..... 111110 ..... ..... @rrx_3 esz=1
MUL_zzx_s 01000100 10 1 ..... 111110 ..... ..... @rrx_2 esz=2
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 0de8445fb4..25dadabe28 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -3866,6 +3866,29 @@ DO_SVE2_RRX(trans_MUL_zzx_d, gen_helper_gvec_mul_idx_d)
#undef DO_SVE2_RRX
+static bool do_sve2_zzxz_ool(DisasContext *s, arg_rrxr_esz *a,
+ gen_helper_gvec_4 *fn)
+{
+ if (!dc_isar_feature(aa64_sve2, s)) {
+ return false;
+ }
+ return do_zzxz_ool(s, a, fn);
+}
+
+#define DO_SVE2_RRXR(NAME, FUNC) \
+ static bool NAME(DisasContext *s, arg_rrxr_esz *a) \
+ { return do_sve2_zzxz_ool(s, a, FUNC); }
+
+DO_SVE2_RRXR(trans_MLA_zzxz_h, gen_helper_gvec_mla_idx_h)
+DO_SVE2_RRXR(trans_MLA_zzxz_s, gen_helper_gvec_mla_idx_s)
+DO_SVE2_RRXR(trans_MLA_zzxz_d, gen_helper_gvec_mla_idx_d)
+
+DO_SVE2_RRXR(trans_MLS_zzxz_h, gen_helper_gvec_mls_idx_h)
+DO_SVE2_RRXR(trans_MLS_zzxz_s, gen_helper_gvec_mls_idx_s)
+DO_SVE2_RRXR(trans_MLS_zzxz_d, gen_helper_gvec_mls_idx_d)
+
+#undef DO_SVE2_RRXR
+
/*
*** SVE Floating Point Multiply-Add Indexed Group
*/
--
2.25.1
- [PATCH v5 52/81] target/arm: Implement SVE2 integer multiply (indexed), (continued)
- [PATCH v5 52/81] target/arm: Implement SVE2 integer multiply (indexed), Richard Henderson, 2021/04/16
- [PATCH v5 58/81] target/arm: Implement SVE2 saturating multiply high (indexed), Richard Henderson, 2021/04/16
- [PATCH v5 54/81] target/arm: Implement SVE2 saturating multiply-add high (indexed), Richard Henderson, 2021/04/16
- [PATCH v5 61/81] target/arm: Implement SVE2 crypto unary operations, Richard Henderson, 2021/04/16
- [PATCH v5 64/81] target/arm: Implement SVE2 TBL, TBX, Richard Henderson, 2021/04/16
- [PATCH v5 60/81] target/arm: Implement SVE mixed sign dot product, Richard Henderson, 2021/04/16
- [PATCH v5 68/81] target/arm: Implement SVE2 FLOGB, Richard Henderson, 2021/04/16
- [PATCH v5 69/81] target/arm: Share table of sve load functions, Richard Henderson, 2021/04/16
- [PATCH v5 62/81] target/arm: Implement SVE2 crypto destructive binary operations, Richard Henderson, 2021/04/16
- [PATCH v5 66/81] target/arm: Implement SVE2 FCVTLT, Richard Henderson, 2021/04/16
- [PATCH v5 53/81] target/arm: Implement SVE2 integer multiply-add (indexed),
Richard Henderson <=
- [PATCH v5 59/81] target/arm: Implement SVE mixed sign dot product (indexed), Richard Henderson, 2021/04/16
- [PATCH v5 65/81] target/arm: Implement SVE2 FCVTNT, Richard Henderson, 2021/04/16
- [PATCH v5 67/81] target/arm: Implement SVE2 FCVTXNT, FCVTX, Richard Henderson, 2021/04/16
- [PATCH v5 63/81] target/arm: Implement SVE2 crypto constructive binary operations, Richard Henderson, 2021/04/16
- [PATCH v5 70/81] target/arm: Implement SVE2 LD1RO, Richard Henderson, 2021/04/16
- [PATCH v5 71/81] target/arm: Implement 128-bit ZIP, UZP, TRN, Richard Henderson, 2021/04/16
- [PATCH v5 72/81] target/arm: Implement SVE2 bitwise shift immediate, Richard Henderson, 2021/04/16
- [PATCH v5 73/81] target/arm: Implement SVE2 fp multiply-add long, Richard Henderson, 2021/04/16
- [PATCH v5 75/81] target/arm: Split out do_neon_ddda_fpst, Richard Henderson, 2021/04/16
- [PATCH v5 74/81] target/arm: Implement aarch64 SUDOT, USDOT, Richard Henderson, 2021/04/16