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[PATCH v5 50/81] target/arm: Split out formats for 2 vectors + 1 index
From: |
Richard Henderson |
Subject: |
[PATCH v5 50/81] target/arm: Split out formats for 2 vectors + 1 index |
Date: |
Fri, 16 Apr 2021 14:02:09 -0700 |
Currently only used by FMUL, but will shortly be used more.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/sve.decode | 14 ++++++++++----
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
index 04ef38f148..a504b55dad 100644
--- a/target/arm/sve.decode
+++ b/target/arm/sve.decode
@@ -67,6 +67,7 @@
&rri_esz rd rn imm esz
&rrri_esz rd rn rm imm esz
&rrr_esz rd rn rm esz
+&rrx_esz rd rn rm index esz
&rpr_esz rd pg rn esz
&rpr_s rd pg rn s
&rprr_s rd pg rn rm s
@@ -245,6 +246,12 @@
@rpri_scatter_store ....... msz:2 .. imm:5 ... pg:3 rn:5 rd:5 \
&rpri_scatter_store
+# Two registers and a scalar by N-bit index
+@rrx_3 ........ .. . .. rm:3 ...... rn:5 rd:5 \
+ &rrx_esz index=%index3_22_19
+@rrx_2 ........ .. . index:2 rm:3 ...... rn:5 rd:5 &rrx_esz
+@rrx_1 ........ .. . index:1 rm:4 ...... rn:5 rd:5 &rrx_esz
+
###########################################################################
# Instruction patterns. Grouped according to the SVE encodingindex.xhtml.
@@ -792,10 +799,9 @@ FMLA_zzxz 01100100 111 index:1 rm:4 00000 sub:1 rn:5
rd:5 \
### SVE FP Multiply Indexed Group
# SVE floating-point multiply (indexed)
-FMUL_zzx 01100100 0.1 .. rm:3 001000 rn:5 rd:5 \
- index=%index3_22_19 esz=1
-FMUL_zzx 01100100 101 index:2 rm:3 001000 rn:5 rd:5 esz=2
-FMUL_zzx 01100100 111 index:1 rm:4 001000 rn:5 rd:5 esz=3
+FMUL_zzx 01100100 0. 1 ..... 001000 ..... ..... @rrx_3 esz=1
+FMUL_zzx 01100100 10 1 ..... 001000 ..... ..... @rrx_2 esz=2
+FMUL_zzx 01100100 11 1 ..... 001000 ..... ..... @rrx_1 esz=3
### SVE FP Fast Reduction Group
--
2.25.1
- [PATCH v5 42/81] target/arm: Implement SVE2 HISTCNT, HISTSEG, (continued)
- [PATCH v5 42/81] target/arm: Implement SVE2 HISTCNT, HISTSEG, Richard Henderson, 2021/04/16
- [PATCH v5 41/81] target/arm: Implement SVE2 RSUBHNB, RSUBHNT, Richard Henderson, 2021/04/16
- [PATCH v5 43/81] target/arm: Implement SVE2 XAR, Richard Henderson, 2021/04/16
- [PATCH v5 44/81] target/arm: Implement SVE2 scatter store insns, Richard Henderson, 2021/04/16
- [PATCH v5 45/81] target/arm: Implement SVE2 gather load insns, Richard Henderson, 2021/04/16
- [PATCH v5 46/81] target/arm: Implement SVE2 FMMLA, Richard Henderson, 2021/04/16
- [PATCH v5 48/81] target/arm: Pass separate addend to {U, S}DOT helpers, Richard Henderson, 2021/04/16
- [PATCH v5 51/81] target/arm: Split out formats for 3 vectors + 1 index, Richard Henderson, 2021/04/16
- [PATCH v5 56/81] target/arm: Implement SVE2 saturating multiply (indexed), Richard Henderson, 2021/04/16
- [PATCH v5 47/81] target/arm: Implement SVE2 SPLICE, EXT, Richard Henderson, 2021/04/16
- [PATCH v5 50/81] target/arm: Split out formats for 2 vectors + 1 index,
Richard Henderson <=
- [PATCH v5 49/81] target/arm: Pass separate addend to FCMLA helpers, Richard Henderson, 2021/04/16
- [PATCH v5 55/81] target/arm: Implement SVE2 saturating multiply-add (indexed), Richard Henderson, 2021/04/16
- [PATCH v5 57/81] target/arm: Implement SVE2 signed saturating doubling multiply high, Richard Henderson, 2021/04/16
- [PATCH v5 52/81] target/arm: Implement SVE2 integer multiply (indexed), Richard Henderson, 2021/04/16
- [PATCH v5 58/81] target/arm: Implement SVE2 saturating multiply high (indexed), Richard Henderson, 2021/04/16
- [PATCH v5 54/81] target/arm: Implement SVE2 saturating multiply-add high (indexed), Richard Henderson, 2021/04/16
- [PATCH v5 61/81] target/arm: Implement SVE2 crypto unary operations, Richard Henderson, 2021/04/16
- [PATCH v5 64/81] target/arm: Implement SVE2 TBL, TBX, Richard Henderson, 2021/04/16
- [PATCH v5 60/81] target/arm: Implement SVE mixed sign dot product, Richard Henderson, 2021/04/16
- [PATCH v5 68/81] target/arm: Implement SVE2 FLOGB, Richard Henderson, 2021/04/16