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[PATCH v5 21/81] target/arm: Implement SVE2 bitwise shift right and accu
From: |
Richard Henderson |
Subject: |
[PATCH v5 21/81] target/arm: Implement SVE2 bitwise shift right and accumulate |
Date: |
Fri, 16 Apr 2021 14:01:40 -0700 |
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/sve.decode | 8 ++++++++
target/arm/translate-sve.c | 34 ++++++++++++++++++++++++++++++++++
2 files changed, 42 insertions(+)
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
index 79046d81e3..d3c4ec6dd1 100644
--- a/target/arm/sve.decode
+++ b/target/arm/sve.decode
@@ -1253,3 +1253,11 @@ UABALT 01000101 .. 0 ..... 1100 11 ..... .....
@rda_rn_rm
# ADC and SBC decoded via size in helper dispatch.
ADCLB 01000101 .. 0 ..... 11010 0 ..... ..... @rda_rn_rm
ADCLT 01000101 .. 0 ..... 11010 1 ..... ..... @rda_rn_rm
+
+## SVE2 bitwise shift right and accumulate
+
+# TODO: Use @rda and %reg_movprfx here.
+SSRA 01000101 .. 0 ..... 1110 00 ..... ..... @rd_rn_tszimm_shr
+USRA 01000101 .. 0 ..... 1110 01 ..... ..... @rd_rn_tszimm_shr
+SRSRA 01000101 .. 0 ..... 1110 10 ..... ..... @rd_rn_tszimm_shr
+URSRA 01000101 .. 0 ..... 1110 11 ..... ..... @rd_rn_tszimm_shr
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 6f5e39b741..c11074cccc 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -6394,3 +6394,37 @@ static bool trans_ADCLT(DisasContext *s, arg_rrrr_esz *a)
{
return do_adcl(s, a, true);
}
+
+static bool do_sve2_fn2i(DisasContext *s, arg_rri_esz *a, GVecGen2iFn *fn)
+{
+ if (a->esz < 0 || !dc_isar_feature(aa64_sve2, s)) {
+ return false;
+ }
+ if (sve_access_check(s)) {
+ unsigned vsz = vec_full_reg_size(s);
+ unsigned rd_ofs = vec_full_reg_offset(s, a->rd);
+ unsigned rn_ofs = vec_full_reg_offset(s, a->rn);
+ fn(a->esz, rd_ofs, rn_ofs, a->imm, vsz, vsz);
+ }
+ return true;
+}
+
+static bool trans_SSRA(DisasContext *s, arg_rri_esz *a)
+{
+ return do_sve2_fn2i(s, a, gen_gvec_ssra);
+}
+
+static bool trans_USRA(DisasContext *s, arg_rri_esz *a)
+{
+ return do_sve2_fn2i(s, a, gen_gvec_usra);
+}
+
+static bool trans_SRSRA(DisasContext *s, arg_rri_esz *a)
+{
+ return do_sve2_fn2i(s, a, gen_gvec_srsra);
+}
+
+static bool trans_URSRA(DisasContext *s, arg_rri_esz *a)
+{
+ return do_sve2_fn2i(s, a, gen_gvec_ursra);
+}
--
2.25.1
- [PATCH v5 07/81] target/arm: Implement SVE2 integer halving add/subtract (predicated), (continued)
- [PATCH v5 07/81] target/arm: Implement SVE2 integer halving add/subtract (predicated), Richard Henderson, 2021/04/16
- [PATCH v5 10/81] target/arm: Implement SVE2 integer add/subtract long, Richard Henderson, 2021/04/16
- [PATCH v5 11/81] target/arm: Implement SVE2 integer add/subtract interleaved long, Richard Henderson, 2021/04/16
- [PATCH v5 12/81] target/arm: Implement SVE2 integer add/subtract wide, Richard Henderson, 2021/04/16
- [PATCH v5 14/81] target/arm: Implement PMULLB and PMULLT, Richard Henderson, 2021/04/16
- [PATCH v5 15/81] target/arm: Implement SVE2 bitwise shift left long, Richard Henderson, 2021/04/16
- [PATCH v5 09/81] target/arm: Implement SVE2 saturating add/subtract (predicated), Richard Henderson, 2021/04/16
- [PATCH v5 13/81] target/arm: Implement SVE2 integer multiply long, Richard Henderson, 2021/04/16
- [PATCH v5 19/81] target/arm: Implement SVE2 integer absolute difference and accumulate long, Richard Henderson, 2021/04/16
- [PATCH v5 17/81] target/arm: Implement SVE2 bitwise permute, Richard Henderson, 2021/04/16
- [PATCH v5 21/81] target/arm: Implement SVE2 bitwise shift right and accumulate,
Richard Henderson <=
- [PATCH v5 16/81] target/arm: Implement SVE2 bitwise exclusive-or interleaved, Richard Henderson, 2021/04/16
- [PATCH v5 18/81] target/arm: Implement SVE2 complex integer add, Richard Henderson, 2021/04/16
- [PATCH v5 22/81] target/arm: Implement SVE2 bitwise shift and insert, Richard Henderson, 2021/04/16
- [PATCH v5 20/81] target/arm: Implement SVE2 integer add/subtract long with carry, Richard Henderson, 2021/04/16
- [PATCH v5 23/81] target/arm: Implement SVE2 integer absolute difference and accumulate, Richard Henderson, 2021/04/16
- [PATCH v5 25/81] target/arm: Implement SVE2 floating-point pairwise, Richard Henderson, 2021/04/16
- [PATCH v5 24/81] target/arm: Implement SVE2 saturating extract narrow, Richard Henderson, 2021/04/16
- [PATCH v5 26/81] target/arm: Implement SVE2 SHRN, RSHRN, Richard Henderson, 2021/04/16
- [PATCH v5 27/81] target/arm: Implement SVE2 SQSHRUN, SQRSHRUN, Richard Henderson, 2021/04/16
- [PATCH v5 28/81] target/arm: Implement SVE2 UQSHRN, UQRSHRN, Richard Henderson, 2021/04/16