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[PATCH v5 0/4] target/arm: Add support for FEAT_TLBIOS and FEAT_TLBIRANG
From: |
Rebecca Cran |
Subject: |
[PATCH v5 0/4] target/arm: Add support for FEAT_TLBIOS and FEAT_TLBIRANGE |
Date: |
Wed, 17 Mar 2021 17:32:57 -0600 |
ARMv8.4 adds the mandatory FEAT_TLBIOS and FEAT_TLBIRANGE.
They provides TLBI maintenance instructions that extend to the Outer
Shareable domain and that apply to a range of input addresses.
Changes from v4 to v5:
o Split changes to cputlb.c and exec_all.c into a separate commit.
o Return a bool from tlb_flush_page_bits_locked to indicate if a full
flush has been done.
o Update flush_page_range_bits_* to exit early when a full flush has
been done.
o Run tb_flush_jmp_cache in a separate loop.
o Don't check for 2 regimes for cases where we know there's only one.
Rebecca Cran (4):
accel/tcg: Add TLB invalidation support for ranges of addresses
target/arm: Add support for FEAT_TLBIRANGE
target/arm: Add support for FEAT_TLBIOS
target/arm: set ID_AA64ISAR0.TLB to 2 for max AARCH64 CPU type
accel/tcg/cputlb.c | 130 ++++++-
include/exec/exec-all.h | 45 +++
target/arm/cpu.h | 10 +
target/arm/cpu64.c | 1 +
target/arm/helper.c | 369 ++++++++++++++++++++
5 files changed, 552 insertions(+), 3 deletions(-)
--
2.26.2
- [PATCH v5 0/4] target/arm: Add support for FEAT_TLBIOS and FEAT_TLBIRANGE,
Rebecca Cran <=
- [PATCH v5 1/4] accel/tcg: Add TLB invalidation support for ranges of addresses, Rebecca Cran, 2021/03/17
- [PATCH v5 3/4] target/arm: Add support for FEAT_TLBIOS, Rebecca Cran, 2021/03/17
- [PATCH v5 4/4] target/arm: set ID_AA64ISAR0.TLB to 2 for max AARCH64 CPU type, Rebecca Cran, 2021/03/17
- [PATCH v5 2/4] target/arm: Add support for FEAT_TLBIRANGE, Rebecca Cran, 2021/03/17
- Re: [PATCH v5 0/4] target/arm: Add support for FEAT_TLBIOS and FEAT_TLBIRANGE, no-reply, 2021/03/17