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[PATCH v4 60/78] target/arm: Implement SVE2 multiply-add long (indexed)
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From: |
Richard Henderson |
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Subject: |
[PATCH v4 60/78] target/arm: Implement SVE2 multiply-add long (indexed) |
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Date: |
Tue, 9 Mar 2021 08:20:23 -0800 |
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/helper-sve.h | 17 +++++++++++++++++
target/arm/sve.decode | 18 ++++++++++++++++++
target/arm/sve_helper.c | 16 ++++++++++++++++
target/arm/translate-sve.c | 20 ++++++++++++++++++++
4 files changed, 71 insertions(+)
diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h
index 548dedf24c..5e3a2922c8 100644
--- a/target/arm/helper-sve.h
+++ b/target/arm/helper-sve.h
@@ -2698,3 +2698,20 @@ DEF_HELPER_FLAGS_4(sve2_sqdmull_idx_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve2_sqdmull_idx_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_5(sve2_smlal_idx_s, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_5(sve2_smlal_idx_d, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_5(sve2_smlsl_idx_s, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_5(sve2_smlsl_idx_d, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_5(sve2_umlal_idx_s, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_5(sve2_umlal_idx_d, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_5(sve2_umlsl_idx_s, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_5(sve2_umlsl_idx_d, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, i32)
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
index 31a3d909f3..c77adf8ca6 100644
--- a/target/arm/sve.decode
+++ b/target/arm/sve.decode
@@ -825,6 +825,24 @@ SQDMLSLB_zzxw_d 01000100 .. 1 ..... 0011.0 ..... .....
@rrxw_d
SQDMLSLT_zzxw_s 01000100 .. 1 ..... 0011.1 ..... ..... @rrxw_s
SQDMLSLT_zzxw_d 01000100 .. 1 ..... 0011.1 ..... ..... @rrxw_d
+# SVE2 multiply-add long (indexed)
+SMLALB_zzxw_s 01000100 .. 1 ..... 1000.0 ..... ..... @rrxw_s
+SMLALB_zzxw_d 01000100 .. 1 ..... 1000.0 ..... ..... @rrxw_d
+SMLALT_zzxw_s 01000100 .. 1 ..... 1000.1 ..... ..... @rrxw_s
+SMLALT_zzxw_d 01000100 .. 1 ..... 1000.1 ..... ..... @rrxw_d
+UMLALB_zzxw_s 01000100 .. 1 ..... 1001.0 ..... ..... @rrxw_s
+UMLALB_zzxw_d 01000100 .. 1 ..... 1001.0 ..... ..... @rrxw_d
+UMLALT_zzxw_s 01000100 .. 1 ..... 1001.1 ..... ..... @rrxw_s
+UMLALT_zzxw_d 01000100 .. 1 ..... 1001.1 ..... ..... @rrxw_d
+SMLSLB_zzxw_s 01000100 .. 1 ..... 1010.0 ..... ..... @rrxw_s
+SMLSLB_zzxw_d 01000100 .. 1 ..... 1010.0 ..... ..... @rrxw_d
+SMLSLT_zzxw_s 01000100 .. 1 ..... 1010.1 ..... ..... @rrxw_s
+SMLSLT_zzxw_d 01000100 .. 1 ..... 1010.1 ..... ..... @rrxw_d
+UMLSLB_zzxw_s 01000100 .. 1 ..... 1011.0 ..... ..... @rrxw_s
+UMLSLB_zzxw_d 01000100 .. 1 ..... 1011.0 ..... ..... @rrxw_d
+UMLSLT_zzxw_s 01000100 .. 1 ..... 1011.1 ..... ..... @rrxw_s
+UMLSLT_zzxw_d 01000100 .. 1 ..... 1011.1 ..... ..... @rrxw_d
+
# SVE2 integer multiply long (indexed)
SMULLB_zzx_s 01000100 .. 1 ..... 1100.0 ..... ..... @rrxl_s
SMULLB_zzx_d 01000100 .. 1 ..... 1100.0 ..... ..... @rrxl_d
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
index 95bda0ae38..c64321368f 100644
--- a/target/arm/sve_helper.c
+++ b/target/arm/sve_helper.c
@@ -1546,6 +1546,20 @@ void HELPER(NAME)(void *vd, void *vn, void *vm, void
*va, uint32_t desc) \
} \
}
+#define DO_MLA(N, M, A) (A + N * M)
+
+DO_ZZXW(sve2_smlal_idx_s, int32_t, int16_t, H1_4, H1_2, DO_MLA)
+DO_ZZXW(sve2_smlal_idx_d, int64_t, int32_t, , H1_4, DO_MLA)
+DO_ZZXW(sve2_umlal_idx_s, uint32_t, uint16_t, H1_4, H1_2, DO_MLA)
+DO_ZZXW(sve2_umlal_idx_d, uint64_t, uint32_t, , H1_4, DO_MLA)
+
+#define DO_MLS(N, M, A) (A - N * M)
+
+DO_ZZXW(sve2_smlsl_idx_s, int32_t, int16_t, H1_4, H1_2, DO_MLS)
+DO_ZZXW(sve2_smlsl_idx_d, int64_t, int32_t, , H1_4, DO_MLS)
+DO_ZZXW(sve2_umlsl_idx_s, uint32_t, uint16_t, H1_4, H1_2, DO_MLS)
+DO_ZZXW(sve2_umlsl_idx_d, uint64_t, uint32_t, , H1_4, DO_MLS)
+
#define DO_SQDMLAL_S(N, M, A) DO_SQADD_S(A, do_sqdmull_s(N, M))
#define DO_SQDMLAL_D(N, M, A) do_sqadd_d(A, do_sqdmull_d(N, M))
@@ -1558,6 +1572,8 @@ DO_ZZXW(sve2_sqdmlal_idx_d, int64_t, int32_t, , H1_4,
DO_SQDMLAL_D)
DO_ZZXW(sve2_sqdmlsl_idx_s, int32_t, int16_t, H1_4, H1_2, DO_SQDMLSL_S)
DO_ZZXW(sve2_sqdmlsl_idx_d, int64_t, int32_t, , H1_4, DO_SQDMLSL_D)
+#undef DO_MLA
+#undef DO_MLS
#undef DO_ZZXW
#define DO_ZZX(NAME, TYPEW, TYPEN, HW, HN, OP) \
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index a3e7d4f38f..6a6698bfe9 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -3940,6 +3940,26 @@ DO_SVE2_RRXR_TB(trans_SQDMLSLB_zzxw_d,
gen_helper_sve2_sqdmlsl_idx_d, false)
DO_SVE2_RRXR_TB(trans_SQDMLSLT_zzxw_s, gen_helper_sve2_sqdmlsl_idx_s, true)
DO_SVE2_RRXR_TB(trans_SQDMLSLT_zzxw_d, gen_helper_sve2_sqdmlsl_idx_d, true)
+DO_SVE2_RRXR_TB(trans_SMLALB_zzxw_s, gen_helper_sve2_smlal_idx_s, false)
+DO_SVE2_RRXR_TB(trans_SMLALB_zzxw_d, gen_helper_sve2_smlal_idx_d, false)
+DO_SVE2_RRXR_TB(trans_SMLALT_zzxw_s, gen_helper_sve2_smlal_idx_s, true)
+DO_SVE2_RRXR_TB(trans_SMLALT_zzxw_d, gen_helper_sve2_smlal_idx_d, true)
+
+DO_SVE2_RRXR_TB(trans_UMLALB_zzxw_s, gen_helper_sve2_umlal_idx_s, false)
+DO_SVE2_RRXR_TB(trans_UMLALB_zzxw_d, gen_helper_sve2_umlal_idx_d, false)
+DO_SVE2_RRXR_TB(trans_UMLALT_zzxw_s, gen_helper_sve2_umlal_idx_s, true)
+DO_SVE2_RRXR_TB(trans_UMLALT_zzxw_d, gen_helper_sve2_umlal_idx_d, true)
+
+DO_SVE2_RRXR_TB(trans_SMLSLB_zzxw_s, gen_helper_sve2_smlsl_idx_s, false)
+DO_SVE2_RRXR_TB(trans_SMLSLB_zzxw_d, gen_helper_sve2_smlsl_idx_d, false)
+DO_SVE2_RRXR_TB(trans_SMLSLT_zzxw_s, gen_helper_sve2_smlsl_idx_s, true)
+DO_SVE2_RRXR_TB(trans_SMLSLT_zzxw_d, gen_helper_sve2_smlsl_idx_d, true)
+
+DO_SVE2_RRXR_TB(trans_UMLSLB_zzxw_s, gen_helper_sve2_umlsl_idx_s, false)
+DO_SVE2_RRXR_TB(trans_UMLSLB_zzxw_d, gen_helper_sve2_umlsl_idx_d, false)
+DO_SVE2_RRXR_TB(trans_UMLSLT_zzxw_s, gen_helper_sve2_umlsl_idx_s, true)
+DO_SVE2_RRXR_TB(trans_UMLSLT_zzxw_d, gen_helper_sve2_umlsl_idx_d, true)
+
#undef DO_SVE2_RRXR_TB
/*
--
2.25.1
- [PATCH v4 59/78] target/arm: Implement SVE2 saturating multiply high (indexed), (continued)
- [PATCH v4 59/78] target/arm: Implement SVE2 saturating multiply high (indexed), Richard Henderson, 2021/03/09
- [PATCH v4 63/78] target/arm: Implement SVE mixed sign dot product, Richard Henderson, 2021/03/09
- [PATCH v4 57/78] target/arm: Implement SVE2 saturating multiply (indexed), Richard Henderson, 2021/03/09
- [PATCH v4 58/78] target/arm: Implement SVE2 signed saturating doubling multiply high, Richard Henderson, 2021/03/09
- [PATCH v4 65/78] target/arm: Implement SVE2 crypto destructive binary operations, Richard Henderson, 2021/03/09
- [PATCH v4 66/78] target/arm: Implement SVE2 crypto constructive binary operations, Richard Henderson, 2021/03/09
- [PATCH v4 67/78] target/arm: Implement SVE2 TBL, TBX, Richard Henderson, 2021/03/09
- [PATCH v4 68/78] target/arm: Implement SVE2 FCVTNT, Richard Henderson, 2021/03/09
- [PATCH v4 64/78] target/arm: Implement SVE2 crypto unary operations, Richard Henderson, 2021/03/09
- [PATCH v4 61/78] target/arm: Implement SVE2 complex integer multiply-add (indexed), Richard Henderson, 2021/03/09
- [PATCH v4 60/78] target/arm: Implement SVE2 multiply-add long (indexed),
Richard Henderson <=
- [PATCH v4 74/78] target/arm: Implement 128-bit ZIP, UZP, TRN, Richard Henderson, 2021/03/09
- [PATCH v4 70/78] target/arm: Implement SVE2 FCVTXNT, FCVTX, Richard Henderson, 2021/03/09
- [PATCH v4 78/78] target/arm: Enable SVE2 and some extensions, Richard Henderson, 2021/03/09
- [PATCH v4 77/78] target/arm: Implement SVE2 complex integer dot product, Richard Henderson, 2021/03/09
- [PATCH v4 72/78] target/arm: Share table of sve load functions, Richard Henderson, 2021/03/09
- [PATCH v4 75/78] target/arm: Implement SVE2 bitwise shift immediate, Richard Henderson, 2021/03/09
- [PATCH v4 69/78] target/arm: Implement SVE2 FCVTLT, Richard Henderson, 2021/03/09
- [PATCH v4 71/78] target/arm: Implement SVE2 FLOGB, Richard Henderson, 2021/03/09
- [PATCH v4 76/78] target/arm: Implement SVE2 fp multiply-add long, Richard Henderson, 2021/03/09
- [PATCH v4 73/78] target/arm: Implement SVE2 LD1RO, Richard Henderson, 2021/03/09