[PATCH v4 0/8] target/arm: sve1 fixes

[Richard Henderson]

Three of these have been hanging around on a queue for ages;
the rest are new.  The WHILE and reduction bugs were found by
RISU triggering an assertion on 384-bit (vq=3) vectors.


r~


Richard Henderson (8):
  target/arm: Fix sve_uzp_p vs odd vector lengths
  target/arm: Fix sve_zip_p vs odd vector lengths
  target/arm: Fix sve_punpk_p vs odd vector lengths
  target/arm: Update find_last_active for PREDDESC
  target/arm: Update BRKA, BRKB, BRKN for PREDDESC
  target/arm: Update CNTP for PREDDESC
  target/arm: Update WHILE for PREDDESC
  target/arm: Update sve reduction vs simd_desc

 target/arm/sve_helper.c    | 107 +++++++++++++++++++++----------------
 target/arm/translate-sve.c |  26 ++++-----
 2 files changed, 73 insertions(+), 60 deletions(-)

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2.25.1