[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [PATCH v2 0/3] target/arm: Restrict v7A TCG cpus to TCG accel
From: |
Philippe Mathieu-Daudé |
Subject: |
Re: [PATCH v2 0/3] target/arm: Restrict v7A TCG cpus to TCG accel |
Date: |
Sat, 6 Mar 2021 16:13:26 +0100 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.7.0 |
On 3/5/21 3:38 PM, Peter Maydell wrote:
> On Sun, 21 Feb 2021 at 22:26, Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>>
>> KVM requires the target cpu to be at least ARMv8 architecture.
>>
>> Restrict the last ARMv7 CPUs (A-profile) to TCG.
>>
>> Series almost fully reviewed (missing review is trivial code style).
>>
>> Since v1: Only include patches which don't depends on previous series
>>
>> Philippe Mathieu-Daudé (3):
>> target/arm: Restrict v8M IDAU to TCG
>> target/arm/cpu: Update coding style to make checkpatch.pl happy
>> target/arm: Restrict v7A TCG cpus to TCG accel
>
> I've applied patches 1 and 2 to target-arm.next, but patch 3 doesn't
> apply (maybe a conflict with something else I've already queued in
> target-arm.next). Could you rebase patch 3 once I've sent out/merged the
> next arm pullreq and resend, please?
This is because of:
commit ed84a60ca80c403749c1fc1bab27c85d8edba39d
Author: Rebecca Cran <rebecca@nuviainc.com>
Date: Tue Feb 16 15:45:43 2021 -0700
target/arm: Set ID_PFR2.SSBS to 1 for "max" 32-bit CPU
Enable FEAT_SSBS for the "max" 32-bit CPU.
Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210216224543.16142-4-rebecca@nuviainc.com
[PMM: fix typo causing compilation failure]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index b8bc89e71fc..058672c9776 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2217,6 +2217,10 @@ static void arm_max_initfn(Object *obj)
t = cpu->isar.id_pfr0;
t = FIELD_DP32(t, ID_PFR0, DIT, 1);
cpu->isar.id_pfr0 = t;
+
+ t = cpu->isar.id_pfr2;
+ t = FIELD_DP32(t, ID_PFR2, SSBS, 1);
+ cpu->isar.id_pfr2 = t;
}
#endif
}
Note this series' patch #3 was following #2. With #2 alone we get:
commit dddc200dcddd1a4e44c32e2b0f5a3cb248c506a6
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: Sun Feb 21 23:26:16 2021 +0100
target/arm/cpu: Update coding style to make checkpatch.pl happy
We will move this code in the next commit. Clean it up
first to avoid checkpatch.pl errors.
With next commit:
commit 9aee50eefba8c39d17759c7def3ba5a899c86271
Author: Peter Maydell <peter.maydell@linaro.org>
Date: Mon Feb 15 10:32:07 2021 +0000
hw/arm/musicpal: Remove dead code for non-32-bit-RGB surfaces
You might want to remove it, or take this series respin, or ignore
this discrepancy in description :)
Thanks,
Phil.