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Re: [PATCH v6 1/5] hw/dma: xlnx_csu_dma: Implement a Xilinx CSU DMA mode
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From: |
Edgar E. Iglesias |
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Subject: |
Re: [PATCH v6 1/5] hw/dma: xlnx_csu_dma: Implement a Xilinx CSU DMA model |
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Date: |
Tue, 2 Mar 2021 16:19:53 +0100 |
On Tue, Mar 02, 2021 at 11:16:10PM +0800, Bin Meng wrote:
> Hi Edgar,
Hi Bin,
>
> On Tue, Mar 2, 2021 at 11:03 PM Edgar E. Iglesias
> <edgar.iglesias@gmail.com> wrote:
> >
> > On Mon, Mar 01, 2021 at 09:20:07PM +0800, Bin Meng wrote:
> > > From: Xuzhou Cheng <xuzhou.cheng@windriver.com>
> > >
> > > ZynqMP QSPI supports SPI transfer using DMA mode, but currently this
....
> > The 3 DONE_CNT bits in R_STATUS need to be w1c so that SW can clear the
> > counter.
> >
> > .w1c = R_STATUS_DONE_CNT_MASK,
> > \
> >
> >
> > For reference, I'm attaching the complete diff I used to pass the testsuite:
> >
>
> Thanks for the review and testing. We will incorporate your diff, test
> and send v7.
>
> Should we include your SoB tag for the diff?
If you take the changes as from my example, you can include:
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Thanks & Best regards,
Edgar
[PATCH v6 3/5] hw/arm: xlnx-zynqmp: Connect a Xilinx CSU DMA module for QSPI, Bin Meng, 2021/03/01
[PATCH v6 4/5] hw/ssi: xilinx_spips: Clean up coding convention issues, Bin Meng, 2021/03/01
[PATCH v6 5/5] hw/ssi: xilinx_spips: Remove DMA related dead codes from zynqmp_spips, Bin Meng, 2021/03/01