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[PATCH 07/11] target/arm: Enforce alignment for VLDR/VSTR
From: |
Richard Henderson |
Subject: |
[PATCH 07/11] target/arm: Enforce alignment for VLDR/VSTR |
Date: |
Tue, 24 Nov 2020 20:06:38 -0800 |
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate-vfp.c.inc | 18 ++++++++++++------
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc
index 58b31ecc3f..51e85c2767 100644
--- a/target/arm/translate-vfp.c.inc
+++ b/target/arm/translate-vfp.c.inc
@@ -926,11 +926,13 @@ static bool trans_VLDR_VSTR_hp(DisasContext *s,
arg_VLDR_VSTR_sp *a)
addr = add_reg_for_lit(s, a->rn, offset);
tmp = tcg_temp_new_i32();
if (a->l) {
- gen_aa32_ld16u(s, tmp, addr, get_mem_index(s));
+ gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s),
+ MO_UW | MO_ALIGN | s->be_data);
vfp_store_reg32(tmp, a->vd);
} else {
vfp_load_reg32(tmp, a->vd);
- gen_aa32_st16(s, tmp, addr, get_mem_index(s));
+ gen_aa32_st_i32(s, tmp, addr, get_mem_index(s),
+ MO_UW | MO_ALIGN | s->be_data);
}
tcg_temp_free_i32(tmp);
tcg_temp_free_i32(addr);
@@ -960,11 +962,13 @@ static bool trans_VLDR_VSTR_sp(DisasContext *s,
arg_VLDR_VSTR_sp *a)
addr = add_reg_for_lit(s, a->rn, offset);
tmp = tcg_temp_new_i32();
if (a->l) {
- gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
+ gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s),
+ MO_UL | MO_ALIGN | s->be_data);
vfp_store_reg32(tmp, a->vd);
} else {
vfp_load_reg32(tmp, a->vd);
- gen_aa32_st32(s, tmp, addr, get_mem_index(s));
+ gen_aa32_st_i32(s, tmp, addr, get_mem_index(s),
+ MO_UL | MO_ALIGN | s->be_data);
}
tcg_temp_free_i32(tmp);
tcg_temp_free_i32(addr);
@@ -1001,11 +1005,13 @@ static bool trans_VLDR_VSTR_dp(DisasContext *s,
arg_VLDR_VSTR_dp *a)
addr = add_reg_for_lit(s, a->rn, offset);
tmp = tcg_temp_new_i64();
if (a->l) {
- gen_aa32_ld64(s, tmp, addr, get_mem_index(s));
+ gen_aa32_ld_i64(s, tmp, addr, get_mem_index(s),
+ MO_Q | MO_ALIGN_4 | s->be_data);
vfp_store_reg64(tmp, a->vd);
} else {
vfp_load_reg64(tmp, a->vd);
- gen_aa32_st64(s, tmp, addr, get_mem_index(s));
+ gen_aa32_st_i64(s, tmp, addr, get_mem_index(s),
+ MO_Q | MO_ALIGN_4 | s->be_data);
}
tcg_temp_free_i64(tmp);
tcg_temp_free_i32(addr);
--
2.25.1
- [PATCH for-6.0 00/11] target/arm: enforce alignment, Richard Henderson, 2020/11/24
- [PATCH 01/11] target/arm: Enforce word alignment for LDRD/STRD, Richard Henderson, 2020/11/24
- [PATCH 02/11] target/arm: Enforce alignment for LDA/LDAH/STL/STLH, Richard Henderson, 2020/11/24
- [PATCH 03/11] target/arm: Enforce alignment for LDM/STM, Richard Henderson, 2020/11/24
- [PATCH 04/11] target/arm: Enforce alignment for RFE, Richard Henderson, 2020/11/24
- [PATCH 05/11] target/arm: Enforce alignment for SRS, Richard Henderson, 2020/11/24
- [PATCH 06/11] target/arm: Enforce alignment for VLDM/VSTM, Richard Henderson, 2020/11/24
- [PATCH 07/11] target/arm: Enforce alignment for VLDR/VSTR,
Richard Henderson <=
- [PATCH 09/11] target/arm: Enforce alignment for VLDn/VSTn (multiple), Richard Henderson, 2020/11/24
- [PATCH 08/11] target/arm: Enforce alignment for VLD1 (all lanes), Richard Henderson, 2020/11/24
- [PATCH 11/11] target/arm: Enforce alignment for VLDn/VSTn (single), Richard Henderson, 2020/11/24
- [PATCH 10/11] target/arm: Fix decode of align in VLDST_single, Richard Henderson, 2020/11/24