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[PATCH 14/17] target/arm: set HPFAR_EL2.NS on secure stage 2 faults
From: |
remi . denis . courmont |
Subject: |
[PATCH 14/17] target/arm: set HPFAR_EL2.NS on secure stage 2 faults |
Date: |
Mon, 23 Nov 2020 10:02:34 +0200 |
From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
---
target/arm/cpu.h | 2 ++
target/arm/helper.c | 6 ++++++
target/arm/internals.h | 2 ++
target/arm/tlb_helper.c | 3 +++
4 files changed, 13 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index a5dd0c5ba4..955f5c34d0 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1482,6 +1482,8 @@ static inline void xpsr_write(CPUARMState *env, uint32_t
val, uint32_t mask)
#define HCR_TWEDEN (1ULL << 59)
#define HCR_TWEDEL MAKE_64BIT_MASK(60, 4)
+#define HPFAR_NS (1ULL << 63)
+
#define SCR_NS (1U << 0)
#define SCR_IRQ (1U << 1)
#define SCR_FIQ (1U << 2)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index d46339f344..86bf0548d9 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -3444,6 +3444,9 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t
value,
target_el = 3;
} else {
env->cp15.hpfar_el2 = extract64(fi.s2addr, 12, 47) << 4;
+ if (arm_is_secure_below_el3(env) && fi.s1ns) {
+ env->cp15.hpfar_el2 |= HPFAR_NS;
+ }
target_el = 2;
}
take_exc = true;
@@ -10446,6 +10449,7 @@ static hwaddr S1_ptw_translate(CPUARMState *env,
ARMMMUIdx mmu_idx,
fi->s2addr = addr;
fi->stage2 = true;
fi->s1ptw = true;
+ fi->s1ns = !*is_secure;
return ~0;
}
if ((arm_hcr_el2_eff(env) & HCR_PTW) &&
@@ -10458,6 +10462,7 @@ static hwaddr S1_ptw_translate(CPUARMState *env,
ARMMMUIdx mmu_idx,
fi->s2addr = addr;
fi->stage2 = true;
fi->s1ptw = true;
+ fi->s1ns = !*is_secure;
return ~0;
}
addr = s2pa;
@@ -11354,6 +11359,7 @@ do_fault:
/* Tag the error as S2 for failed S1 PTW at S2 or ordinary S2. */
fi->stage2 = fi->s1ptw || (mmu_idx == ARMMMUIdx_Stage2 ||
mmu_idx == ARMMMUIdx_Stage2_S);
+ fi->s1ns = mmu_idx == ARMMMUIdx_Stage2;
return true;
}
diff --git a/target/arm/internals.h b/target/arm/internals.h
index 5205e3ad8d..c1fc679c18 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -593,6 +593,7 @@ typedef enum ARMFaultType {
* @s2addr: Address that caused a fault at stage 2
* @stage2: True if we faulted at stage 2
* @s1ptw: True if we faulted at stage 2 while doing a stage 1 page-table walk
+ * @s1ns: True if we faulted on a non-secure IPA while in secure state
* @ea: True if we should set the EA (external abort type) bit in syndrome
*/
typedef struct ARMMMUFaultInfo ARMMMUFaultInfo;
@@ -603,6 +604,7 @@ struct ARMMMUFaultInfo {
int domain;
bool stage2;
bool s1ptw;
+ bool s1ns;
bool ea;
};
diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c
index b35dc8a011..df85079d9f 100644
--- a/target/arm/tlb_helper.c
+++ b/target/arm/tlb_helper.c
@@ -63,6 +63,9 @@ static void QEMU_NORETURN arm_deliver_fault(ARMCPU *cpu,
vaddr addr,
if (fi->stage2) {
target_el = 2;
env->cp15.hpfar_el2 = extract64(fi->s2addr, 12, 47) << 4;
+ if (arm_is_secure_below_el3(env) && fi->s1ns) {
+ env->cp15.hpfar_el2 |= HPFAR_NS;
+ }
}
same_el = (arm_current_el(env) == target_el);
--
2.29.2
- [PATCH 03/17] target/arm: use arm_is_el2_enabled() where applicable, (continued)
- [PATCH 03/17] target/arm: use arm_is_el2_enabled() where applicable, remi . denis . courmont, 2020/11/23
- [PATCH 04/17] target/arm: use arm_hcr_el2_eff() where applicable, remi . denis . courmont, 2020/11/23
- [PATCH 10/17] target/arm: add ARMv8.4-SEL2 system registers, remi . denis . courmont, 2020/11/23
- [PATCH 06/17] target/arm: declare new AA64PFR0 bit-fields, remi . denis . courmont, 2020/11/23
- [PATCH 07/17] target/arm: add 64-bit S-EL2 to EL exception table, remi . denis . courmont, 2020/11/23
- [PATCH 08/17] target/arm: return the stage 2 index for stage 1, remi . denis . courmont, 2020/11/23
- [PATCH 09/17] target/arm: add MMU stage 1 for Secure EL2, remi . denis . courmont, 2020/11/23
- [PATCH 13/17] target/arm: handle VMID change in secure state, remi . denis . courmont, 2020/11/23
- [PATCH 11/17] target/arm: do S1_ptw_translate() before address space lookup, remi . denis . courmont, 2020/11/23
- [PATCH 16/17] target/arm: enable Secure EL2 in max CPU, remi . denis . courmont, 2020/11/23
- [PATCH 14/17] target/arm: set HPFAR_EL2.NS on secure stage 2 faults,
remi . denis . courmont <=
- [PATCH 15/17] target/arm: add ARMv8.4-SEL2 extension, remi . denis . courmont, 2020/11/23
- [PATCH 12/17] target/arm: secure stage 2 translation regime, remi . denis . courmont, 2020/11/23
- [PATCH 17/17] target/arm: refactor vae1_tlbmask(), remi . denis . courmont, 2020/11/23