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[PATCH v2 03/28] target/arm: Don't clobber ID_PFR1.Security on M-profile
From: |
Peter Maydell |
Subject: |
[PATCH v2 03/28] target/arm: Don't clobber ID_PFR1.Security on M-profile cores |
Date: |
Thu, 19 Nov 2020 21:55:52 +0000 |
In arm_cpu_realizefn() we check whether the board code disabled EL3
via the has_el3 CPU object property, which we create if the CPU
starts with the ARM_FEATURE_EL3 feature bit. If it is disabled, then
we turn off ARM_FEATURE_EL3 and also zero out the relevant fields in
the ID_PFR1 and ID_AA64PFR0 registers.
This codepath was incorrectly being taken for M-profile CPUs, which
do not have an EL3 and don't set ARM_FEATURE_EL3, but which may have
the M-profile Security extension and so should have non-zero values
in the ID_PFR1.Security field.
Restrict the handling of the feature flag to A/R-profile cores.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 07492e9f9a4..40f3f798b2b 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1674,7 +1674,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error
**errp)
}
}
- if (!cpu->has_el3) {
+ if (!arm_feature(env, ARM_FEATURE_M) && !cpu->has_el3) {
/* If the has_el3 CPU property is disabled then we need to disable the
* feature.
*/
--
2.20.1
- [PATCH v2 00/28] target/arm: Implement v8.1M and Cortex-M55, Peter Maydell, 2020/11/19
- [PATCH v2 02/28] target/arm: Implement v8.1M PXN extension, Peter Maydell, 2020/11/19
- [PATCH v2 03/28] target/arm: Don't clobber ID_PFR1.Security on M-profile cores,
Peter Maydell <=
- [PATCH v2 04/28] target/arm: Implement VSCCLRM insn, Peter Maydell, 2020/11/19
- [PATCH v2 01/28] hw/intc/armv7m_nvic: Make all of system PPB range be RAZWI/BusFault, Peter Maydell, 2020/11/19
- [PATCH v2 05/28] target/arm: Implement CLRM instruction, Peter Maydell, 2020/11/19
- [PATCH v2 06/28] target/arm: Enforce M-profile VMRS/VMSR register restrictions, Peter Maydell, 2020/11/19
- [PATCH v2 07/28] target/arm: Refactor M-profile VMSR/VMRS handling, Peter Maydell, 2020/11/19
- [PATCH v2 09/28] target/arm: Implement VLDR/VSTR system register, Peter Maydell, 2020/11/19
- [PATCH v2 08/28] target/arm: Move general-use constant expanders up in translate.c, Peter Maydell, 2020/11/19
- [PATCH v2 11/28] target/arm: Use new FPCR_NZCV_MASK constant, Peter Maydell, 2020/11/19
- [PATCH v2 12/28] target/arm: Factor out preserve-fp-state from full_vfp_access_check(), Peter Maydell, 2020/11/19