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Re: [PATCH v2 09/15] hw/misc/bcm2835_cprman: implement PLL channels beha
From: |
Philippe Mathieu-Daudé |
Subject: |
Re: [PATCH v2 09/15] hw/misc/bcm2835_cprman: implement PLL channels behaviour |
Date: |
Tue, 6 Oct 2020 11:07:22 +0200 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.11.0 |
On 10/5/20 9:56 PM, Luc Michel wrote:
> A PLL channel is able to further divide the generated PLL frequency.
> The divider is given in the CTRL_A2W register. Some channels have an
> additional fixed divider which is always applied to the signal.
>
> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> Signed-off-by: Luc Michel <luc@lmichel.fr>
> ---
> hw/misc/bcm2835_cprman.c | 33 ++++++++++++++++++++++++++++++++-
> 1 file changed, 32 insertions(+), 1 deletion(-)
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
- Re: [PATCH v2 10/15] hw/misc/bcm2835_cprman: add a clock mux skeleton implementation, (continued)
- [PATCH v2 11/15] hw/misc/bcm2835_cprman: implement clock mux behaviour, Luc Michel, 2020/10/05
- [PATCH v2 12/15] hw/misc/bcm2835_cprman: add the DSI0HSCK multiplexer, Luc Michel, 2020/10/05
- [PATCH v2 15/15] hw/arm/bcm2835_peripherals: connect the UART clock, Luc Michel, 2020/10/05
- [PATCH v2 13/15] hw/misc/bcm2835_cprman: add sane reset values to the registers, Luc Michel, 2020/10/05
- [PATCH v2 09/15] hw/misc/bcm2835_cprman: implement PLL channels behaviour, Luc Michel, 2020/10/05
- Re: [PATCH v2 09/15] hw/misc/bcm2835_cprman: implement PLL channels behaviour,
Philippe Mathieu-Daudé <=
- [PATCH v2 14/15] hw/char/pl011: add a clock input, Luc Michel, 2020/10/05