Re: [PATCH 21/22] target/arm: Implement VFP fp16 VMOV between gp and halfprec registers

[Richard Henderson]

On 8/24/20 7:29 AM, Peter Maydell wrote:
> Implement the VFP fp16 variant of VMOV that transfers a 16-bit
> value between a general purpose register and a VFP register.
> 
> Note that Rt == 15 is UNPREDICTABLE; since this insn is v8 and later
> only we have no need to replicate the old "updates CPSR.NZCV"
> behaviour that the singleprec version of this insn does.
> 
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
>  target/arm/vfp.decode          |  1 +
>  target/arm/translate-vfp.c.inc | 34 ++++++++++++++++++++++++++++++++++
>  2 files changed, 35 insertions(+)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~